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    DAC
    1996
    ACM
    105views Computer Architecture» more  DAC 1996»
    Design Considerations and Tools for Low-voltage Digital System Design
    13 years 8 months ago
    Design Considerations and Tools for Low-voltage Digital System Design
    Download  www.cs.york.ac.uk
    Aggressive voltage scaling to 1V and below through technology, circuit, and architecture optimization has been proven to be the key to ultra low-power design. The key technology t...
    Anantha Chandrakasan, Isabel Yang, Carlin Vieri, D...
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    DAC
    1996
    ACM
    78views Computer Architecture» more  DAC 1996»
    State Reduction Using Reversible Rules
    13 years 8 months ago
    State Reduction Using Reversible Rules
    Download  www.cs.york.ac.uk
    We reduce the state explosion problem in automatic verification of finite-state systems by automatically collapsing subgraphs of the aph into abstract states. The key idea of the ...
    C. Norris Ip, David L. Dill
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    DAC
    1996
    ACM
    103views Computer Architecture» more  DAC 1996»
    Techniques for Verifying Superscalar Microprocessors
    13 years 8 months ago
    Techniques for Verifying Superscalar Microprocessors
    Download  www.cs.york.ac.uk
    Burch and Dill [3] described an automatic method for verifying a pipelined processor against its instruction setarchitecture(ISA). We describethree techniquesfor improving this me...
    Jerry R. Burch
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    DAC
    1996
    ACM
    115views Computer Architecture» more  DAC 1996»
    Bit-Level Analysis of an SRT Divider Circuit
    13 years 8 months ago
    Bit-Level Analysis of an SRT Divider Circuit
    Download  www.cs.cmu.edu
    Abstract-- It is impractical to verify multiplier or divider circuits entirely at the bit-level using ordered Binary Decision Diagrams (BDDs), because the BDD representations for t...
    Randal E. Bryant
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    DAC
    1996
    ACM
    98views Computer Architecture» more  DAC 1996»
    Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools
    13 years 8 months ago
    Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools
    Download  www.eecg.toronto.edu
    This paper provides a case study that shows how a demanding application stresses the capabilities of today's CAD tools, especially in the integration of products from multipl...
    Stephen Dean Brown, Naraig Manjikian, Zvonko G. Vr...
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    DAC
    1996
    ACM
    83views Computer Architecture» more  DAC 1996»
    Power Estimation of Cell-Based CMOS Circuits
    13 years 8 months ago
    Power Estimation of Cell-Based CMOS Circuits
    Download  www.cs.york.ac.uk
    PPP is a Web-based simulation and synthesis environment for low-power design. In this paper we describe the gate-level simulation engine of PPP, that achieves accuracy always with...
    Alessandro Bogliolo, Luca Benini, Bruno Ricc&ograv...
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    DAC
    1996
    ACM
    156views Computer Architecture» more  DAC 1996»
    A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts
    13 years 8 months ago
    A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts
    Download  www.cs.york.ac.uk
    Abstract -- This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Specific Integrated Pro...
    Nguyen-Ngoc Bình, Masaharu Imai, Akichika S...
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    DAC
    1996
    ACM
    150views Computer Architecture» more  DAC 1996»
    Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis
    13 years 8 months ago
    Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis
    Download  www.cs.york.ac.uk
    This paper presents the design of a Videophone CoderDecoder Motion Estimator using two High-Level Synthesis tools. Indeed, the combination of a Control Flow Dominated part (comple...
    Elisabeth Berrebi, Polen Kission, Serge Vernalde, ...
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    DAC
    1996
    ACM
    103views Computer Architecture» more  DAC 1996»
    An O(n) Algorithm for Transistor Stacking with Performance Constraints
    13 years 8 months ago
    An O(n) Algorithm for Transistor Stacking with Performance Constraints
    Download  www.jos.org.cn
    Bulent Basaran, Rob A. Rutenbar
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    DAC
    1996
    ACM
    271views Computer Architecture» more  DAC 1996»
    Functional Verification Methodology of Chameleon Processor
    13 years 8 months ago
    Functional Verification Methodology of Chameleon Processor
    Download  www.cs.york.ac.uk
    - Functional verification of the new generation microprocessor developed by SGS-THOMSON Microelectronics makes extensive use of advanced technologies. This paper presents a global ...
    Françoise Casaubieilh, Anthony McIsaac, Mik...
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