Sciweavers

DAC
1997
ACM
13 years 8 months ago
Potential-Driven Statistical Ordering of Transformations
Inki Hong, Darko Kirovski, Miodrag Potkonjak
DAC
1997
ACM
13 years 8 months ago
Safe BDD Minimization Using Don't Cares
In many computer-aided design tools, binary decision diagrams (BDDs) are used to represent Boolean functions. To increase the efficiency and capability of these tools, many algor...
Youpyo Hong, Peter A. Beerel, Jerry R. Burch, Kenn...
DAC
1997
ACM
13 years 8 months ago
Dynamic Communication Models in Embedded System Co-Simulation
Many co-simulation techniques either suffer from poor performance when simulating communications intensive systems, or they represent communications with a uniformly low level of ...
Ken Hines, Gaetano Borriello
DAC
1997
ACM
13 years 8 months ago
Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign
An experimental set of tools that generate instruction set simulators, assemblers, and disassemblers from a single description was developed to test if retargetable development to...
Mark R. Hartoog, James A. Rowson, Prakash D. Reddy...
DAC
1997
ACM
13 years 8 months ago
Frequency-Domain Compatibility in Digital Filter BIST
We examine frequency-domain issues in the design and selection of on-chip test generators for built-in self-test (BIST) of highperformance digital filters. Test-generator/circuit...
Laurence Goodby, Alex Orailoglu
DAC
1997
ACM
13 years 8 months ago
ISDL: An Instruction Set Description Language for Retargetability
Abstract—We present the Instruction Set Description Language, ISDL, a machine description language used to describe target architectures to a retargetable compiler. The features ...
George Hadjiyiannis, Silvina Hanono, Srinivas Deva...
DAC
1997
ACM
13 years 8 months ago
Power Macromodeling for High Level Power Estimation
A modeling approach is presented that captures the dependence of the power dissipation of a combinational logic circuit on its input output signal switching activity. The resulting...
Subodh Gupta, Farid N. Najm
DAC
1997
ACM
13 years 8 months ago
Toward Formalizing a Validation Methodology Using Simulation Coverage
The biggest obstacle in the formal verification of large designs is their very large state spaces, which cannot be handled even by techniques such as implicit state space travers...
Aarti Gupta, Sharad Malik, Pranav Ashar
DAC
1997
ACM
13 years 8 months ago
CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells
We present a novel technique CLIP for optimizing both the height and width of CMOS cell layouts in the two-dimensional (2D) style. CLIP is based on integer-linear programming (ILP...
Avaneendra Gupta, John P. Hayes