Sciweavers

DAC
2000
ACM
13 years 8 months ago
Removing user specified false paths from timing graphs
David Blaauw, Rajendran Panda, Abhijit Das
DAC
2000
ACM
13 years 8 months ago
Modeling and simulation of real defects using fuzzy logic
Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. In this paper we first show that the trad...
Amir Attarha, Mehrdad Nourani, Caro Lucas
DAC
2000
ACM
13 years 8 months ago
TACO: timing analysis with coupling
: The impact of coupling capacitance on delay is usually estimated by scaling the coupling capacitances (often by a factor of 2) and modeling them as grounded. This simple approach...
Ravishankar Arunachalam, Karthik Rajagopal, Lawren...
DAC
2000
ACM
14 years 5 months ago
Hierarchical analysis of power distribution networks
Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, T...
DAC
2000
ACM
14 years 5 months ago
System chip test: how will it impact your design?
A major challenge in realizing core-based system chips is the adoption and design-in of adequate test and diagnosis strategies. This tutorial paper discusses the specific challeng...
Yervant Zorian, Erik Jan Marinissen
DAC
2000
ACM
14 years 5 months ago
The use of carry-save representation in joint module selection and retiming
Joint module selection and retiming is a powerful technique to optimize the implementation cost and the speed of a circuit specified using a synchronous data-flow graph (DFG). In ...
Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.
DAC
2000
ACM
14 years 5 months ago
The design and use of simplepower: a cycle-accurate energy estimation tool
In this paper, we presen t the design and use of a comprehensiv e framework, SimplePower, for evaluating the e ect of high-level algorithmic, architectural, and compilation tradeo...
Wu Ye, Narayanan Vijaykrishnan, Mahmut T. Kandemir...
DAC
2000
ACM
14 years 5 months ago
MINFLOTRANSIT: min-cost flow based transistor sizing tool
This paper presents MINFLOTRANSIT, a new transistor sizing tool for fast sizing of combinational circuits with minimal cost. MINFLOTRANSIT is an iterative relaxation based tool th...
Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K...