Sciweavers

DAC
2001
ACM
14 years 5 months ago
Route Packets, Not Wires: On-Chip Interconnection Networks
Using on-chip interconnection networks in place of ad-hoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules...
William J. Dally, Brian Towles
DAC
2001
ACM
14 years 5 months ago
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping
In this paper, we study the problem of performance-driven multi-level circuit clustering with application to hierarchical FPGA designs. We first show that the performance-driven m...
Jason Cong, Michail Romesis
DAC
2001
ACM
14 years 5 months ago
A New Gate Delay Model for Simultaneous Switching and Its Applications
Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
DAC
2001
ACM
14 years 5 months ago
Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods
In this paper, we propose preconditioned Krylov-subspace iterative methods to perform efficient DC and transient simulations for large-scale linear circuits with an emphasis on po...
Tsung-Hao Chen, Charlie Chung-Ping Chen
DAC
2001
ACM
14 years 5 months ago
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during manufacturing testing. External testing for crosstalk is expensive ...
Li Chen, Xiaoliang Bai, Sujit Dey
DAC
2001
ACM
14 years 5 months ago
Creating and Exploiting Flexibility in Steiner Trees
This paper presents the concept of flexibility ? a geometric property associated with Steiner trees. Flexibility is related to the routability of the Steiner tree. We present an o...
Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzade...
DAC
2001
ACM
14 years 5 months ago
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
Kaustav Banerjee, Amit Mehrotra
DAC
2001
ACM
14 years 5 months ago
Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs
Non-uniform temperature profiles along global interconnect lines in high-performance ICs can significantly impact the performance of these lines. This paper presents a detailed an...
Amir H. Ajami, Kaustav Banerjee, Massoud Pedram, L...