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    DAC
    2003
    ACM
    113views Computer Architecture» more  DAC 2003»
    Optimizations for a simulator construction system supporting reusable components
    14 years 5 months ago
    Optimizations for a simulator construction system supporting reusable components
    Download  bardd.ee.byu.edu
    Exploring a large portion of the microprocessor design space requires the rapid development of efficient simulators. While some systems support rapid model development through the...
    David A. Penry, David I. August
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    DAC
    2003
    ACM
    161views Computer Architecture» more  DAC 2003»
    Design of a 10GHz clock distribution network using coupled standing-wave oscillators
    14 years 5 months ago
    Design of a 10GHz clock distribution network using coupled standing-wave oscillators
    Download  www.ece.ucsb.edu
    Frank O'Mahony, C. Patrick Yue, Mark Horowitz, S. ...
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    DAC
    2003
    ACM
    138views Computer Architecture» more  DAC 2003»
    Instruction encoding synthesis for architecture exploration using hierarchical processor models
    14 years 5 months ago
    Instruction encoding synthesis for architecture exploration using hierarchical processor models
    Download  www.coware.com
    This paper presents a novel instruction encoding generation technique for use in architecture exploration for application specific processors. The underlying exploration methodolo...
    Achim Nohl, Volker Greive, Gunnar Braun, Andreas H...
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    DAC
    2003
    ACM
    191views Computer Architecture» more  DAC 2003»
    A retargetable micro-architecture simulator
    14 years 5 months ago
    A retargetable micro-architecture simulator
    Download  www.eecg.toronto.edu
    The capability of performing architectural exploration has become essential for embedded microprocessor design in System-On-Chip. While many retargetable instruction set (ISA) sim...
    Wai Sum Mong, Jianwen Zhu
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    DAC
    2003
    ACM
    111views Computer Architecture» more  DAC 2003»
    Power-aware issue queue design for speculative instructions
    14 years 5 months ago
    Power-aware issue queue design for speculative instructions
    Download  www.swarthmore.edu
    Speculatively issued instructions may be particularly sensitive to increases in pipeline depth. Our results indicate that as pipeline depth increases, speculation increases the pe...
    Tali Moreshet, R. Iris Bahar
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    DAC
    2003
    ACM
    129views Computer Architecture» more  DAC 2003»
    A new enhanced constructive decomposition and mapping algorithm
    14 years 5 months ago
    A new enhanced constructive decomposition and mapping algorithm
    Download  www.eecs.berkeley.edu
    Structuring and mapping of a Boolean function is an important problem in the design of complex integrated circuits. Libraryaware constructive decomposition offers a solution to th...
    Alan Mishchenko, Xinning Wang, Timothy Kam
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    DAC
    2003
    ACM
    129views Computer Architecture» more  DAC 2003»
    Large-scale SOP minimization using decomposition and functional properties
    14 years 5 months ago
    Large-scale SOP minimization using decomposition and functional properties
    Download  www.eecs.berkeley.edu
    In some cases, minimum Sum-Of-Products (SOP) expressions of Boolean functions can be derived by detecting decomposition and observing the functional properties such as unateness, ...
    Alan Mishchenko, Tsutomu Sasao
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    DAC
    2003
    ACM
    164views Computer Architecture» more  DAC 2003»
    A transformation based algorithm for reversible logic synthesis
    14 years 5 months ago
    A transformation based algorithm for reversible logic synthesis
    Download  www.cs.unb.ca
    A digital combinational logic circuit is reversible if it maps each input pattern to a unique output pattern. Such circuits are of interest in quantum computing, optical computing...
    D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck
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    DAC
    2003
    ACM
    106views Computer Architecture» more  DAC 2003»
    A tool for describing and evaluating hierarchical real-time bus scheduling policies
    14 years 5 months ago
    A tool for describing and evaluating hierarchical real-time bus scheduling policies
    Download  cadal.cse.nsysu.edu.tw
    We present a tool suite for building, simulating, and analyzing the results of hierarchical descriptions of the scheduling policy for modules sharing a bus in real-time applicatio...
    Trevor Meyerowitz, Claudio Pinello, Alberto L. San...
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    DAC
    2003
    ACM
    148views Computer Architecture» more  DAC 2003»
    Global resource sharing for synthesis of control data flow graphs on FPGAs
    14 years 5 months ago
    Global resource sharing for synthesis of control data flow graphs on FPGAs
    Download  www.utdallas.edu
    Seda Ogrenci Memik, Gokhan Memik, Roozbeh Jafari, ...
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