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DAC
2003
ACM
9 years 11 months ago
Optimizations for a simulator construction system supporting reusable components
Exploring a large portion of the microprocessor design space requires the rapid development of efficient simulators. While some systems support rapid model development through the...
David A. Penry, David I. August
DAC
2003
ACM
9 years 11 months ago
Instruction encoding synthesis for architecture exploration using hierarchical processor models
This paper presents a novel instruction encoding generation technique for use in architecture exploration for application specific processors. The underlying exploration methodolo...
Achim Nohl, Volker Greive, Gunnar Braun, Andreas H...
DAC
2003
ACM
9 years 11 months ago
A retargetable micro-architecture simulator
The capability of performing architectural exploration has become essential for embedded microprocessor design in System-On-Chip. While many retargetable instruction set (ISA) sim...
Wai Sum Mong, Jianwen Zhu
DAC
2003
ACM
9 years 11 months ago
Power-aware issue queue design for speculative instructions
Speculatively issued instructions may be particularly sensitive to increases in pipeline depth. Our results indicate that as pipeline depth increases, speculation increases the pe...
Tali Moreshet, R. Iris Bahar
DAC
2003
ACM
9 years 11 months ago
A new enhanced constructive decomposition and mapping algorithm
Structuring and mapping of a Boolean function is an important problem in the design of complex integrated circuits. Libraryaware constructive decomposition offers a solution to th...
Alan Mishchenko, Xinning Wang, Timothy Kam
DAC
2003
ACM
9 years 11 months ago
Large-scale SOP minimization using decomposition and functional properties
In some cases, minimum Sum-Of-Products (SOP) expressions of Boolean functions can be derived by detecting decomposition and observing the functional properties such as unateness, ...
Alan Mishchenko, Tsutomu Sasao
DAC
2003
ACM
9 years 11 months ago
A transformation based algorithm for reversible logic synthesis
A digital combinational logic circuit is reversible if it maps each input pattern to a unique output pattern. Such circuits are of interest in quantum computing, optical computing...
D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck
DAC
2003
ACM
9 years 11 months ago
A tool for describing and evaluating hierarchical real-time bus scheduling policies
We present a tool suite for building, simulating, and analyzing the results of hierarchical descriptions of the scheduling policy for modules sharing a bus in real-time applicatio...
Trevor Meyerowitz, Claudio Pinello, Alberto L. San...
DAC
2003
ACM
9 years 11 months ago
Global resource sharing for synthesis of control data flow graphs on FPGAs
Seda Ogrenci Memik, Gokhan Memik, Roozbeh Jafari, ...
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