Sciweavers

DAC
2005
ACM
13 years 6 months ago
Asynchronous circuits transient faults sensitivity evaluation
1 This paper presents a transient faults sensitivity evaluation for Quasi Delay Insensitive (QDI) asynchronous circuits. Because of their specific architecture, asynchronous circui...
Yannick Monnet, Marc Renaudin, Régis Leveug...
DAC
2005
ACM
13 years 6 months ago
Logic soft errors in sub-65nm technologies design and CAD challenges
Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches) and combinational logic. Robust enterprise platforms in sub-65nm technolog...
Subhasish Mitra, Tanay Karnik, Norbert Seifert, Mi...
DAC
2005
ACM
13 years 6 months ago
Multiplexer restructuring for FPGA implementation cost reduction
This paper presents a novel synthesis algorithm that reduces the area needed for implementing multiplexers on an FPGA by an average of 18%. This is achieved by reducing the number...
Paul Metzgen, Dominic Nancekievill
DAC
2005
ACM
13 years 6 months ago
Matlab extensions for the development, testing and verification of real-time DSP software
The purpose of this paper is to present the required tools for the development, testing and verification of DSP software in Matlab. The paper motivates a DSP Simulator concept tha...
David P. Magee
DAC
2005
ACM
13 years 6 months ago
Partitioning-based approach to fast on-chip decap budgeting and minimization
This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in today’s ...
Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, ...
DAC
2005
ACM
13 years 6 months ago
Cognitive radio techniques for wide area networks
The cellular wireless market has begun the transition to data centric services including high speed internet access, video, high quality audio, and gaming. Communications technolo...
William Krenik, Anuj Batra
DAC
2005
ACM
13 years 6 months ago
Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
Ho Young Kim, Tag Gon Kim
DAC
2005
ACM
13 years 6 months ago
Design methodology for IC manufacturability based on regular logic-bricks
Implementing logic blocks in an integrated circuit in terms of repeating or regular geometry patterns [6,7] can provide significant advantages in terms of manufacturability and de...
V. Kheterpal, V. Rovner, T. G. Hersan, D. Motiani,...
DAC
2005
ACM
13 years 6 months ago
Path delay test compaction with process variation tolerance
In this paper we propose a test compaction method for path delay faults in a logic circuit. The method generates a compact set of two-pattern tests for faults on long paths select...
Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, T...
DAC
2005
ACM
13 years 6 months ago
Prime clauses for fast enumeration of satisfying assignments to boolean circuits
Finding all satisfying assignments of a propositional formula has many applications in the design of hardware and software. An approach to this problem augments a clause-recording...
HoonSang Jin, Fabio Somenzi