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DAC
2006
ACM
9 years 6 months ago
SystemC transaction level models and RTL verification
This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are bei...
Stuart Swan
DAC
2006
ACM
9 years 6 months ago
"The IC nanometer race -- what will it take to win?"
: Creating ICs in the nanometer age is a high-stakes race that few companies can afford to compete in – and even fewer can win. Hear how senior technologists from the world’s t...
G. Singer, Philippe Magarshack, Dennis Buss, F.-C....
DAC
2006
ACM
9 years 6 months ago
DFM: where's the proof of value?
How can design teams employ new tools and develop response methodologies yet still stay within design budgets? How much effort does it require to be an early adopter and what kind...
Shishpal Rawat, Raul Camposano, A. Kahng, Joseph S...
DAC
2006
ACM
9 years 6 months ago
The zen of nonvolatile memories
Silicon technology based nonvolatile memories (NVM) have achieved widespread adoption for code and data storage applications. In the last 30 years, the traditional floating gate ...
Erwin J. Prinz
DAC
2006
ACM
9 years 6 months ago
Practical aspects of reliability analysis for IC designs
T. Pompl, C. Schlünder, M. Hommel, H. Nielen,...
DAC
2006
ACM
9 years 6 months ago
A CMOS SoC for 56/18/16 CD/DVD-dual/RAM applications
Jyh-Shin Pan, Hao-Cheng Chen, Bing-Yu Hsieh, Hong-...
DAC
2006
ACM
9 years 6 months ago
Mining global constraints for improving bounded sequential equivalence checking
In this paper, we propose a novel technique on mining relationships in a sequential circuit to discover global constraints. In contrast to the traditional learning methods, our mi...
Weixin Wu, Michael S. Hsiao
DAC
2006
ACM
9 years 6 months ago
Modeling and analysis of circuit performance of ballistic CNFET
With the advent of carbon nanotube technology, evaluating circuit and system performance using these devices is becoming extremely important. In this paper, we propose a quasi-ana...
Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Tho...
DAC
2006
ACM
9 years 6 months ago
Variation-aware analysis: savior of the nanometer era?
VLSI engineers have traditionally used a variety of CAD analysis tools (e.g. SPICE) to deal with variability. As we go into deep sub micron issues, the analysis is becoming harder...
Sani R. Nassif, Vijay Pitchumani, N. Rodriguez, De...
DAC
2006
ACM
9 years 6 months ago
Signature-based workload estimation for mobile 3D graphics
Until recently, most 3D graphics applications had been regarded as too computationally intensive for devices other than desktop computers and gaming consoles. This notion is rapid...
Bren Mochocki, Kanishka Lahiri, Srihari Cadambi, X...
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