Sciweavers

Share
DAC
2006
ACM
10 years 11 months ago
Register binding for clock period minimization
Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei...
DAC
2006
ACM
10 years 11 months ago
Exploring compromises among timing, power and temperature in three-dimensional integrated circuits
Three-dimensional integrated circuits (3DICs) have the potential to reduce interconnect lengths and improve digital system performance. However, heat removal is more difficult in ...
Hao Hua, Christopher Mineo, Kory Schoenfliess, Amb...
DAC
2006
ACM
10 years 11 months ago
Communication latency aware low power NoC synthesis
Yuanfang Hu, Yi Zhu, Hongyu Chen, Ronald L. Graham...
DAC
2006
ACM
10 years 11 months ago
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
Yu Hu, Yan Lin, Lei He, Tim Tuan
DAC
2006
ACM
10 years 11 months ago
Fast algorithms for slew constrained minimum cost buffering
As a prevalent constraint, sharp slew rate is often required in circuit design which causes a huge demand for buffering resources. This problem requires ultra-fast buffering techn...
Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K...
DAC
2006
ACM
10 years 11 months ago
Efficient simulation of critical synchronous dataflow graphs
Simulation and verification using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems. The synchronous dat...
Chia-Jui Hsu, José Luis Pino, Ming-Yung Ko,...
DAC
2006
ACM
10 years 11 months ago
Power-centric design of high-speed I/Os
With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is const...
Hamid Hatamkhani, Frank Lambrecht, Vladimir Stojan...
DAC
2006
ACM
10 years 11 months ago
Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM
Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source...
Swaroop Ghosh, Saibal Mukhopadhyay, Kee-Jong Kim, ...
DAC
2006
ACM
10 years 11 months ago
Rapid estimation of control delay from high-level specifications
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...
Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda
books