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DAC
2006
ACM
10 years 1 months ago
Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs
Multimedia applications usually have throughput constraints. An implementation must meet these constraints, while it minimizes resource usage and energy consumption. The compute i...
Sander Stuijk, Marc Geilen, Twan Basten
DAC
2006
ACM
10 years 1 months ago
FLAW: FPGA lifetime awareness
Aggressive scaling of technology has an adverse impact on the reliability of VLSI circuits. Apart from increasing transient error susceptibility, the circuits also become more vul...
Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie,...
DAC
2006
ACM
10 years 1 months ago
Synthesis of high-performance packet processing pipelines
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...
Cristian Soviani, Ilija Hadzic, Stephen A. Edwards
DAC
2006
ACM
10 years 1 months ago
Statistical timing analysis with correlated non-gaussian parameters using independent component analysis
We propose a scalable and efficient parameterized block-based statistical static timing analysis algorithm incorporating both Gaussian and non-Gaussian parameter distributions, ca...
Jaskirat Singh, Sachin S. Sapatnekar
DAC
2006
ACM
10 years 1 months ago
Gain-based technology mapping for minimum runtime leakage under input vector uncertainty
The gain-based technology mapping paradigm has been successfully employed for finding minimum delay and minimum area mappings. However, existing gain-based technology mappers fail...
Ashish Kumar Singh, Murari Mani, Ruchir Puri, Mich...
DAC
2006
ACM
10 years 1 months ago
Circuit simulation based obstacle-aware Steiner routing
Steiner routing is a fundamental yet NP-hard problem in VLSI design and other research fields. In this paper, we propose to model the routing graph by an RC network with routing t...
Yiyu Shi, Paul Mesa, Hao Yu, Lei He
DAC
2006
ACM
10 years 1 months ago
Optimal cell flipping in placement and floorplanning
In a placed circuit, there are a lot of movable cells that can be flipped to further reduce the total wirelength, without affecting the original placement solution. We aim at solv...
Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N...
DAC
2006
ACM
10 years 1 months ago
Efficient SAT-based Boolean matching for FPGA technology mapping
Most FPGA technology mapping approaches either target Lookup Tables (LUTs) or relatively simple Programmable Logic Blocks (PLBs). Considering networks of PLBs during technology map...
Sean Safarpour, Andreas G. Veneris, Gregg Baeckler...
DAC
2006
ACM
10 years 1 months ago
Topology aware mapping of logic functions onto nanowire-based crossbar architectures
Highly regular, nanodevice based architectures have been proposed to replace pure CMOS based architectures in the emerging post CMOS era. Since bottom-up self-assembly is used to ...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
DAC
2006
ACM
10 years 1 months ago
A new hybrid FPGA with nanoscale clusters and CMOS routing
In this paper we propose a hybrid FPGA using nanoscale clusters with an architecture similar to clusters of traditional CMOS FPGAs. The proposed cluster is made of a crossbar of n...
Reza M. Rad, Mohammad Tehranipoor
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