Sciweavers

DAC
2010
ACM
13 years 7 months ago
Trace-driven optimization of networks-on-chip configurations
Networks-on-chip (NoCs) are becoming increasingly important in general-purpose and application-specific multi-core designs. Although uniform router configurations are appropriate ...
Andrew B. Kahng, Bill Lin, Kambiz Samadi, Rohit Su...
DAC
2010
ACM
13 years 7 months ago
On the costs and benefits of stochasticity in stream processing
With the end of clock-frequency scaling, parallelism has emerged as the key driver of chip-performance growth. Yet, several factors undermine efficient simultaneous use of onchip ...
Raj R. Nadakuditi, Igor L. Markov
DAC
2010
ACM
13 years 7 months ago
Scalable specification mining for verification and diagnosis
Effective system verification requires good specifications. The lack of sufficient specifications can lead to misses of critical bugs, design re-spins, and time-to-market slips. I...
Wenchao Li, Alessandro Forin, Sanjit A. Seshia
DAC
2010
ACM
13 years 8 months ago
Quality metric evaluation of a physical unclonable function derived from an IC's power distribution system
The level of security provided by digital rights management functions and cryptographic protocols depend heavily on the security of an embedded secret key. The current practice of...
Ryan Helinski, Dhruva Acharyya, Jim Plusquellic
DAC
2010
ACM
13 years 8 months ago
Cost-aware three-dimensional (3D) many-core multiprocessor design
The emerging three-dimensional integrated circuit (3D IC) is beneficial for various applications from both area and performance perspectives. While the general trend in processor...
Jishen Zhao, Xiangyu Dong, Yuan Xie
DAC
2010
ACM
13 years 8 months ago
Networks on Chips: from research to products
Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address th...
Giovanni De Micheli, Ciprian Seiculescu, Srinivasa...
DAC
2010
ACM
13 years 8 months ago
An efficient algorithm to verify generalized false paths
Timing exception verification has become a center of interest as incorrect constraints can lead to chip failures. Proving that a false path is valid or not is a difficult problem ...
Olivier Coudert