DAC
2010
ACM
13 years 8 months ago
2010
ACM
State-of-the-art automatic reliability analyses as used in system-level design approaches mainly rely on Binary Decision Diagrams (BDDs) and, thus, face two serious problems: (1) ...
DAC
2010
ACM
13 years 8 months ago
2010
ACM
DAC
2010
ACM
13 years 8 months ago
2010
ACM
Understanding the flow of information is an important aspect in computer security. There has been a recent move towards tracking information in hardware and understanding the flow...
DAC
2010
ACM
13 years 8 months ago
2010
ACM
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
DAC
2010
ACM
13 years 8 months ago
2010
ACM
With the ever-increasing transistor variability in CMOS technology, it is essential to integrate variation-aware performance analysis into the task allocation and scheduling proce...
DAC
2010
ACM
13 years 8 months ago
2010
ACM
Current tools for computer architecture design lack standard support for multi- and many-core development. We propose using circuit models to describe the multiple processor archi...
DAC
2010
ACM
13 years 8 months ago
2010
ACM
Clock skew optimization continues to be an important concern in circuit designs. To overcome the influence caused by PVT variations, the automatic skew synchronization scheme can ...
DAC
2010
ACM
13 years 8 months ago
2010
ACM
DAC
2010
ACM
13 years 8 months ago
2010
ACM
—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NP-hard ...
DAC
2010
ACM
13 years 8 months ago
2010
ACM
In this paper we summarize recent developments in compact dynamical modeling for both linear and nonlinear systems arising in analog applications. These techniques include methods...