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DATE
1999
IEEE
118views Hardware» more  DATE 1999»
9 years 3 months ago
Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits
Estimating peak power involves optimization of the circuit's switching function. We propose genetic spot expansion and optimization in this paper to estimate tight peak power...
Michael S. Hsiao
DATE
1999
IEEE
139views Hardware» more  DATE 1999»
9 years 3 months ago
OpenJ: An Extensible System Level Design Language
There is an increasing research interest in system level design languages which can carry designers from specification to implementation of system-on-a-chip. Unfortunately, two of...
Jianwen Zhu, Daniel Gajski
DATE
1999
IEEE
72views Hardware» more  DATE 1999»
9 years 3 months ago
On Programmable Memory Built-In Self Test Architectures
The design and architectures of a microcode-based memory BIST and programmable FSM-based memory BIST unit are presented. The proposed microcode-based memory BIST unit is more e ci...
Kamran Zarrineh, Shambhu J. Upadhyaya
DATE
1999
IEEE
113views Hardware» more  DATE 1999»
9 years 3 months ago
Cycle-based Simulation with Decision Diagrams
This paper addresses the problem of efficient functional simulation of synchronous digital systems. A technique based on the use of Decision Diagrams (DD) for representing the fun...
Raimund Ubar, Jaan Raik, Adam Morawiec
DATE
1999
IEEE
112views Hardware» more  DATE 1999»
9 years 3 months ago
Fast Hardware-Software Co-simulation Using VHDL Models
Bassam Tabbara, Marco Sgroi, Alberto L. Sangiovann...
DATE
1999
IEEE
101views Hardware» more  DATE 1999»
9 years 3 months ago
Polynomial Methods for Allocating Complex Components
Methods for performing component matching by expressing an arithmetic specification and a bit-level description of an implementation as word-level polynomials have been demonstrat...
James Smith, Giovanni De Micheli
DATE
1999
IEEE
194views Hardware» more  DATE 1999»
9 years 3 months ago
Algorithms for Solving Boolean Satisfiability in Combinational Circuits
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation, It finds application in test pattern generation, delay-fault testing, combinational equivalen...
Luís Guerra e Silva, Luis Miguel Silveira, ...
DATE
1999
IEEE
85views Hardware» more  DATE 1999»
9 years 3 months ago
At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks
As an at-speed solution to board-level interconnect testing, an enhanced boundary-scan architecture utilizing a combination of slightly modified boundary-scan cells and a user-def...
Jongchul Shin, Hyunjin Kim, Sungho Kang
DATE
1999
IEEE
147views Hardware» more  DATE 1999»
9 years 3 months ago
Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints
In this paper, a method for the automatic sizing of analog integrated circuits is presented. Basic sizing rules, representing circuit knowledge, are set up before the sizing and a...
Robert Schwencker, Josef Eckmueller, Helmut E. Gra...
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
9 years 3 months ago
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
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