DATE
1999
IEEE
13 years 8 months ago
1999
IEEE
DATE
1999
IEEE
13 years 8 months ago
1999
IEEE
Software programming languages, such as C/C++, have been used as means for specifying hardware for quite a while. Different design methodologies have exploited the advantages of f...
DATE
1999
IEEE
13 years 8 months ago
1999
IEEE
Different logic synthesis tasks have been formulated as input encoding problems but restricted to use a minimum number of binary variables. This paper presents an original column ...
DATE
1999
IEEE
13 years 8 months ago
1999
IEEE
The problem of checking the equivalence of combinational circuits is of key significance in the verification of digital circuits. In recent years, several approaches have been pro...
DATE
1999
IEEE
1999
IEEE
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs
13 years 8 months ago
This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization ...
DATE
1999
IEEE
13 years 8 months ago
1999
IEEE
We introduce a novel behavioral test synthesis methodology that attempts to increase module reachability, driven by powerful global design path analysis. Based on the notion of tr...
DATE
1999
IEEE
13 years 8 months ago
1999
IEEE
DATE
1999
IEEE
13 years 8 months ago
1999
IEEE
This paper investigates retiming and clock skew scheduling for improving the tolerance of synchronous circuits to delay variations. It is shown that when both long and short paths...
DATE
1999
IEEE
13 years 8 months ago
1999
IEEE
Power estimation is important for system-level exploration and trade-off analysis of VLSI systems. A power estimator for high-speed analog to digital converters that exploits info...
DATE
1999
IEEE
13 years 8 months ago
1999
IEEE
Commonly used scheduling algorithms in high-level synthesis only accept one process at a time and are not capable of sharing resources across process boundaries. This results in t...