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DATE
1999
IEEE
56views Hardware» more  DATE 1999»
9 years 4 months ago
Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization
Enrique San Millán, Luis Entrena, Jos&eacut...
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
9 years 4 months ago
Hardware Synthesis from C/C++ Models
Software programming languages, such as C/C++, have been used as means for specifying hardware for quite a while. Different design methodologies have exploited the advantages of f...
Giovanni De Micheli
DATE
1999
IEEE
123views Hardware» more  DATE 1999»
9 years 4 months ago
An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length
Different logic synthesis tasks have been formulated as input encoding problems but restricted to use a minimum number of binary variables. This paper presents an original column ...
Manuel Martínez, Maria J. Avedillo, Jos&eac...
DATE
1999
IEEE
135views Hardware» more  DATE 1999»
9 years 4 months ago
Combinational Equivalence Checking Using Satisfiability and Recursive Learning
The problem of checking the equivalence of combinational circuits is of key significance in the verification of digital circuits. In recent years, several approaches have been pro...
João P. Marques Silva, Thomas Glass
DATE
1999
IEEE
123views Hardware» more  DATE 1999»
9 years 4 months ago
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs
This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization ...
Nazanin Mansouri, Ranga Vemuri
DATE
1999
IEEE
73views Hardware» more  DATE 1999»
9 years 4 months ago
Channel-Based Behavioral Test Synthesis for Improved Module Reachability
We introduce a novel behavioral test synthesis methodology that attempts to increase module reachability, driven by powerful global design path analysis. Based on the notion of tr...
Yiorgos Makris, Alex Orailoglu
DATE
1999
IEEE
62views Hardware» more  DATE 1999»
9 years 4 months ago
Kernel Scheduling in Reconfigurable Computing
Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh...
DATE
1999
IEEE
127views Hardware» more  DATE 1999»
9 years 4 months ago
Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits
This paper investigates retiming and clock skew scheduling for improving the tolerance of synchronous circuits to delay variations. It is shown that when both long and short paths...
Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
DATE
1999
IEEE
81views Hardware» more  DATE 1999»
9 years 4 months ago
A Power Estimation Model for High-Speed CMOS A/D Converters
Power estimation is important for system-level exploration and trade-off analysis of VLSI systems. A power estimator for high-speed analog to digital converters that exploits info...
Erik Lauwers, Georges G. E. Gielen
DATE
1999
IEEE
80views Hardware» more  DATE 1999»
9 years 4 months ago
Time Constrained Modulo Scheduling with Global Resource Sharing
Commonly used scheduling algorithms in high-level synthesis only accept one process at a time and are not capable of sharing resources across process boundaries. This results in t...
Christoph Jäschke, Rainer Laur, Friedrich Bec...
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