DATE
2000
IEEE
13 years 8 months ago
2000
IEEE
In this paper, an analysis of test time by CBET (which is an acronym for Combination of BIST and External Test) test approach is presented. The analysis validates that CBET test a...
DATE
2000
IEEE
13 years 8 months ago
2000
IEEE
This paper proposes an all digital on-chip bus delay and crosstalk measurement methodology. A diagnosis procedure is derived to distinguish the delay faults in drivers, receivers,...
DATE
2000
IEEE
13 years 8 months ago
2000
IEEE
DATE
2000
IEEE
13 years 8 months ago
2000
IEEE
DATE
2000
IEEE
13 years 8 months ago
2000
IEEE
Recently a number of heuristic based system-level synthesis algorithms have been proposed. Though these algorithms quickly generate good solutions, how close these solutions are t...
DATE
2000
IEEE
13 years 8 months ago
2000
IEEE
A novel method which can be regarded as the noisecounterpart of the celebrated Elmore’s delay formula— both being based on the first two moments of the network’s transfer fu...
DATE
2000
IEEE
13 years 8 months ago
2000
IEEE
-- One of the greatest challenges in C/C++-based design methodology is to efficiently map C/C++ models into hardware. Many of the networking and multimedia applications implemente...
DATE
2000
IEEE
13 years 8 months ago
2000
IEEE
Pass Transistor Logic has attracted more and more interest during last years, since it has proved to be an attractive alternative to static CMOS designs with respect to area, perf...
DATE
2000
IEEE
13 years 8 months ago
2000
IEEE
Passive components integrated into a high-density substrate can be a tolerable way to overcome the size and manufacturing limits of SMD passives mounted onto the system board. Sti...
DATE
2000
IEEE
13 years 8 months ago
2000
IEEE
Process variation has forever been the major fail cause of analog circuit where small deviations in component values cause large deviations in the measured output parameters. This...