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DATE
2000
IEEE
77views Hardware» more  DATE 2000»
13 years 8 months ago
Designing Closer to the Edge
Sani R. Nassif
DATE
2000
IEEE
94views Hardware» more  DATE 2000»
13 years 8 months ago
Shared Memory Implementations of Synchronous Dataflow Specifications
There has been a proliferation of block-diagram environments for specifying and prototyping DSP systems. These include tools from academia like Ptolemy [3], and GRAPE [7], and com...
Praveen K. Murthy, Shuvra S. Bhattacharyya
DATE
2000
IEEE
103views Hardware» more  DATE 2000»
13 years 8 months ago
Protocol Stack-Based Telecom-Emulator
The paper describes the concept and implementation of a telecom emulator that features both recon gurability and high-speed processing. The emulator can be easily transmuted into ...
Takahiro Murooka, Toshiaki Miyazaki
DATE
2000
IEEE
114views Hardware» more  DATE 2000»
13 years 8 months ago
Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths
Designs which do not fully utilize their arithmetic datapath components typically exhibit a significant overhead in power consumption. Whenever a module performs an operation who...
Michael Münch, Norbert Wehn, Bernd Wurth, Ren...
DATE
2000
IEEE
114views Hardware» more  DATE 2000»
13 years 8 months ago
On Using Satisfiability-Based Pruning Techniques in Covering Algorithms
Vasco M. Manquinho, João P. Marques Silva
DATE
2000
IEEE
83views Hardware» more  DATE 2000»
13 years 8 months ago
Wave Steered FSMs
In this paper we address the problem of designing very high throughput finite state machines (FSMs). The presence of loops in sequential circuits prevents a straightforward and g...
Luca Macchiarulo, Shih-Ming Shu, Malgorzata Marek-...
DATE
2000
IEEE
88views Hardware» more  DATE 2000»
13 years 8 months ago
Techniques for Reducing Read Latency of Core Bus Wrappers
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...
Roman L. Lysecky, Frank Vahid, Tony Givargis
DATE
2000
IEEE
140views Hardware» more  DATE 2000»
13 years 8 months ago
Parallel and Distributed VHDL Simulation
This paper presents a methodology for parallel and distributed simulation of VHDL using the PDES (parallel discrete-event simulation) paradigm. To achieve better features and perf...
Dragos Lungeanu, C.-J. Richard Shi
DATE
2000
IEEE
112views Hardware» more  DATE 2000»
13 years 8 months ago
Quantitative Comparison of Power Management Algorithms
Dynamic power management saves power by shutting down idle devices. Several management algorithms have been proposed and demonstrated effective in certain applications. We quantit...
Yung-Hsiang Lu, Eui-Young Chung, Tajana Simunic, G...