DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
The composite signal flow model of computation targets systems with significant control and data processing parts. It builds on the data flow and synchronous data flow models ...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper is about gate sizing under a statistical delay model. It shows we can solve the gate sizing problem exactly for a given statistical delay model. The formulation used al...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper, we present a BIST scheme for testing onchip AD and DA converters. We discuss on-chip generation of linear ramps as test stimuli, and propose techniques for measurin...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
– A split-bus architecture is proposed to improve the power dissipation for global data exchange among a set of modules. The resulting bus splitting problem is formulated and sol...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
As the CMOS technology scaled down, the horizontal coupling capacitance between adjacent wires plays dominant part in wire load, crosstalk interference becomes a serious problem f...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper examines several techniques for static timing analysis. In detail, the first part of the paper analyzes the connection of prediction accuracy (worst case execution tim...