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DATE
2002
IEEE
84views Hardware» more  DATE 2002»
13 years 9 months ago
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
Gilles Sassatelli, Lionel Torres, Pascal Benoit, T...
DATE
2002
IEEE
118views Hardware» more  DATE 2002»
13 years 9 months ago
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures
: A new technique is presented in this paper to improve the efficiency of data scheduling for multi-context reconfigurable architectures targeting multimedia and DSP applications. ...
Marcos Sanchez-Elez, Milagros Fernández, Ra...
DATE
2002
IEEE
114views Hardware» more  DATE 2002»
13 years 9 months ago
A Video Compression Case Study on a Reconfigurable VLIW Architecture
In this paper, we investigate the benefits of a flexible, application-specific instruction set by adding a run-time Reconfigurable Functional Unit (RFU) to a VLIW processor. Preli...
Davide Rizzo, Osvaldo Colavin
DATE
2002
IEEE
166views Hardware» more  DATE 2002»
13 years 9 months ago
Event Model Interfaces for Heterogeneous System Analysis
Complex embedded systems consist of hardware and software components from different domains, such as control and signal processing, many of them supplied by different IP vendors. ...
Kai Richter, Rolf Ernst
DATE
2002
IEEE
96views Hardware» more  DATE 2002»
13 years 9 months ago
Embedded System Design Based On Webservices
The structure of Internet applications and scenarios is changing rapidly today. This offers new potential for established technologies and methods to expand their area of applicat...
Achim Rettberg, Wolfgang Thronicke
DATE
2002
IEEE
135views Hardware» more  DATE 2002»
13 years 9 months ago
Reducing Test Application Time Through Test Data Mutation Encoding
In this paper we propose a new compression algorithm geared to reduce the time needed to test scan-based designs. Our scheme compresses the test vector set by encoding the bits th...
Sherief Reda, Alex Orailoglu
DATE
2002
IEEE
98views Hardware» more  DATE 2002»
13 years 9 months ago
A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits
A unified approach to fault simulation for FGDs is introduced. Instead of a direct fault simulation, the proposed approach calculates indirectly from the simulator output the set...
Michael Pronath, Helmut E. Graeb, Kurt Antreich
DATE
2002
IEEE
124views Hardware» more  DATE 2002»
13 years 9 months ago
Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits
In this paper we introduce an approach for parameter controlled symbolic analysis of nonlinear analog circuits. Based on a state-of–the-art algorithm, it enables the removal of ...
Ralf Popp, Joerg Oehmen, Lars Hedrich, Erich Barke
DATE
2002
IEEE
100views Hardware» more  DATE 2002»
13 years 9 months ago
AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors
This paper describes the AccuPower toolset -- a set of simulation tools accurately estimating the power dissipation within a superscalar microprocessor. AccuPower uses a true hard...
Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
DATE
2002
IEEE
114views Hardware» more  DATE 2002»
13 years 9 months ago
Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults
Test sets for path delay faults in circuits with large numbers of paths are typically generated for path delay faults associated with the longest circuit paths. We show that such ...
Irith Pomeranz, Sudhakar M. Reddy