Sciweavers

DATE
2002
IEEE
161views Hardware» more  DATE 2002»
13 years 9 months ago
Hardware/Software Trade-Offs for Advanced 3G Channel Coding
Third generation’s wireless communications systems comprise advanced signal processing algorithms that increase the computational requirements more than ten-fold over 2G’s sys...
Heiko Michel, Alexander Worm, Norbert Wehn, Michae...
DATE
2002
IEEE
98views Hardware» more  DATE 2002»
13 years 9 months ago
Self-Checking Scheme for the On-Line Testing of Power Supply Noise
Cecilia Metra, Luca Schiano, Bruno Riccò, M...
DATE
2002
IEEE
138views Hardware» more  DATE 2002»
13 years 9 months ago
Automatic Evaluation of the Accuracy of Fixed-Point Algorithms
The minimization of cost, power consumption and timeto-market of DSP applications requires the development of methodologies for the automatic implementation of floating-point alg...
Daniel Menard, Olivier Sentieys
DATE
2002
IEEE
119views Hardware» more  DATE 2002»
13 years 9 months ago
UML for Embedded Systems Specification and Design: Motivation and Overview
The specification, design and implementation of embedded systems demands new approaches which go beyond traditional hardware-based notations such as HDLs. The growing dominance of...
Grant Martin
DATE
2002
IEEE
120views Hardware» more  DATE 2002»
13 years 9 months ago
Wire Placement for Crosstalk Energy Minimization in Address Buses
We propose a novel approach to bus energy minimization that targets crosstalk effects. Unlike previous approaches, we try to reduce energy through capacitance optimization, by ad ...
Luca Macchiarulo, Enrico Macii, Massimo Poncino
DATE
2002
IEEE
114views Hardware» more  DATE 2002»
13 years 9 months ago
An Adaptive Dictionary Encoding Scheme for SOC Data Buses
Tiehan Lv, Wayne Wolf, Jörg Henkel, Haris Lek...
DATE
2002
IEEE
69views Hardware» more  DATE 2002»
13 years 9 months ago
Flip-Flop and Repeater Insertion for Early Interconnect Planning
We present a unified framework that considers flipflop and repeater insertion and the placement of flipflop/repeater blocks during RT or higher level design. We introduce the...
Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan C...
DATE
2002
IEEE
135views Hardware» more  DATE 2002»
13 years 9 months ago
A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications
This paper focuses on I-cache behaviour enhancement through the application of high-level code transformations. Specifically, a flow for the iterative application of the I-Cache pe...
Nikolaos D. Liveris, Nikolaos D. Zervas, Dimitrios...
DATE
2002
IEEE
128views Hardware» more  DATE 2002»
13 years 9 months ago
Arbitrary Convex and Concave Rectilinear Module Packing Using TCG
In this paper, we deal with arbitrary convex and concave rectilinear module packing using the Transitive Closure Graph (TCG) representation. The geometric meanings of modules are ...
Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang