Sciweavers

DATE
2002
IEEE
95views Hardware» more  DATE 2002»
13 years 8 months ago
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem
Abstract—Antenna problem is a phenomenon of plasma-induced gateoxide degradation. It directly affects manufacturability of very large scale integration (VLSI) circuits, especiall...
Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong,...
DATE
2002
IEEE
74views Hardware» more  DATE 2002»
13 years 8 months ago
Maze Routing with Buffer Insertion under Transition Time Constraints
In this paper, we address the problem of simultaneous routing and buffer insertion. Recently in [12, 22], the authors considered simultaneous maze routing and buffer insertion und...
Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao
DATE
2002
IEEE
84views Hardware» more  DATE 2002»
13 years 8 months ago
Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory
Multimedia applications are characterized by a large number of data accesses and complex array index manipulations. The built-in address decoder in the RAM memory model commonly u...
Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas...
DATE
2002
IEEE
75views Hardware» more  DATE 2002»
13 years 8 months ago
System Design for Flexibility
With the term flexibility, we introduce a new design dimension of an embedded system that quantitatively characterizes its feasibility in implementing not only one, but possibly ...
Christian Haubelt, Jürgen Teich, Kai Richter,...
DATE
2002
IEEE
69views Hardware» more  DATE 2002»
13 years 8 months ago
Verifying Clock Schedules in the Presence of Cross Talk
This paper addresses verifying the timing of circuits containing level-sensitive latches in the presence of cross talk. We show that three consecutive periodic occurrences of the ...
Soha Hassoun, Eduardo Calvillo-Gámez, Chris...
DATE
2002
IEEE
63views Hardware» more  DATE 2002»
13 years 8 months ago
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs
Ashok Halambi, Aviral Shrivastava, Partha Biswas, ...
DATE
2002
IEEE
115views Hardware» more  DATE 2002»
13 years 8 months ago
Design Technology for Networked Reconfigurable FPGA Platforms
Future networked appliances should be able to download new services or upgrades from the network and execute them locally. This flexibility is typically achieved by processors tha...
Steve Guccione, Diederik Verkest, Ivo Bolsens
DATE
2002
IEEE
97views Hardware» more  DATE 2002»
13 years 8 months ago
Analog IP Testing: Diagnosis and Optimization
In this paper, we present an innovative methodology to estimate and improve the quality of analog and mixed-signal circuit testing. We first detect and reduce the redundancy in th...
Carlo Guardiani, Patrick McNamara, Lidia Daldoss, ...
DATE
2002
IEEE
83views Hardware» more  DATE 2002»
13 years 8 months ago
Memory System Connectivity Exploration
In programmable embedded systems, the memory subsystem represents a major cost, performance and power bottleneck. To optimize the system for such different goals, the designer wou...
Peter Grun, Nikil D. Dutt, Alexandru Nicolau