Sciweavers

DATE
2004
IEEE
156views Hardware» more  DATE 2004»
13 years 8 months ago
Timing Analysis for Preemptive Multi-Tasking Real-Time Systems with Caches
In this paper, we propose an approach to estimate the Worst Case Response Time (WCRT) of tasks in a preemptive multi-tasking single-processor real-time system with a set associati...
Yudong Tan, Vincent John Mooney III
DATE
2004
IEEE
131views Hardware» more  DATE 2004»
13 years 8 months ago
Testing of Quantum Dot Cellular Automata Based Designs
There has been considerable research on quantum dots cellular automata as a new computing scheme in the nano-scale regimes. The basic logic element of this technology is a majorit...
Mehdi Baradaran Tahoori, Fabrizio Lombardi
DATE
2004
IEEE
105views Hardware» more  DATE 2004»
13 years 8 months ago
Time-Energy Design Space Exploration for Multi-Layer Memory Architectures
This paper presents an exploration algorithm which examines execution time and energy consumption of a given application, while considering a parameterized memory architecture. Th...
Radoslaw Szymanek, Francky Catthoor, Krzysztof Kuc...
DATE
2004
IEEE
173views Hardware» more  DATE 2004»
13 years 8 months ago
Supporting Cache Coherence in Heterogeneous Multiprocessor Systems
In embedded system-on-a-chip (SoC) applications, the need for integrating heterogeneous processors in a single chip is increasing. An important issue in integrating heterogeneous ...
Taeweon Suh, Douglas M. Blough, Hsien-Hsin S. Lee
DATE
2004
IEEE
164views Hardware» more  DATE 2004»
13 years 8 months ago
System Design Using Kahn Process Networks: The Compaan/Laura Approach
New emerging embedded system platforms in the realm of highthroughput multimedia, imaging, and signal processing will consist of multiple microprocessors and reconfigurable compon...
Todor Stefanov, Claudiu Zissulescu, Alexandru Turj...
DATE
2004
IEEE
125views Hardware» more  DATE 2004»
13 years 8 months ago
Local Decisions and Triggering Mechanisms for Adaptive Fault-Tolerance
Dynamic fault-tolerance management (DFTM) was previously introduced as a means of providing environmentand workload-driven adaptation for failure-prone battery powered systems. Th...
Phillip Stanley-Marbell, Diana Marculescu
DATE
2004
IEEE
132views Hardware» more  DATE 2004»
13 years 8 months ago
Hybrid Architectural Dynamic Thermal Management
When an application or external environmental conditions cause a chip's cooling capacity to be exceeded, dynamic thermal management (DTM) dynamically reduces the power densit...
Kevin Skadron
DATE
2004
IEEE
126views Hardware» more  DATE 2004»
13 years 8 months ago
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...
Montek Singh, Michael Theobald
DATE
2004
IEEE
158views Hardware» more  DATE 2004»
13 years 8 months ago
Communication Analysis for System-On-Chip Design
In this paper we present an approach for analysis of systems of parallel, communicating processes for SoC design. We present a method to detect communications that synchronize the...
Axel Siebenborn, Oliver Bringmann, Wolfgang Rosens...
DATE
2004
IEEE
136views Hardware» more  DATE 2004»
13 years 8 months ago
Compact Binaries with Code Compression in a Software Dynamic Translator
Embedded software is becoming more flexible and adaptable, which presents new challenges for management of highly constrained system resources. Software dynamic translation is a t...
Stacey Shogan, Bruce R. Childers