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DATE
2005
IEEE
141views Hardware» more  DATE 2005»
8 years 7 months ago
Multimedia Applications of Multiprocessor Systems-on-Chips
This paper surveys the characteristics of multimedia systems. Multimedia applications today are dominated by compression and decompression, but multimedia devices must also implem...
Wayne Wolf
DATE
2005
IEEE
111views Hardware» more  DATE 2005»
8 years 7 months ago
MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumptio
This paper proposes a novel architecture synthesis algorithm for single-loop single-bit ∆Σ modulators. We defined a generic modulator architecture and derived its noise and si...
Hua Tang, Ying Wei, Alex Doboli
DATE
2005
IEEE
111views Hardware» more  DATE 2005»
8 years 7 months ago
Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures
In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consump...
Suresh Srinivasan, Lin Li, Narayanan Vijaykrishnan
DATE
2005
IEEE
120views Hardware» more  DATE 2005»
8 years 7 months ago
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance
This paper reports a novel simulation methodology for analysis and prediction of substrate noise impact on analog / RF circuits taking into account the role of the parasitic resis...
Charlotte Soens, Geert Van der Plas, Piet Wambacq,...
DATE
2005
IEEE
138views Hardware» more  DATE 2005»
8 years 7 months ago
BB-GC: Basic-Block Level Garbage Collection
Memory space limitation is a serious problem for many embedded systems from diverse application domains. While circuit/packaging techniques are definitely important to squeeze la...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin
DATE
2005
IEEE
164views Hardware» more  DATE 2005»
8 years 7 months ago
Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture
Transaction Level Modeling (TLM) approach is used to meet the simulation speed as well as cycle accuracy for large scale SoC performance analysis. We implemented a transaction-lev...
Young-Taek Kim, Taehun Kim, Youngduk Kim, Chulho S...
DATE
2005
IEEE
176views Hardware» more  DATE 2005»
8 years 7 months ago
LORD: A Localized, Reactive and Distributed Protocol for Node Scheduling in Wireless Sensor Networks
The lifetime of wireless sensor networks can be increased by minimizing the number of active nodes that provide complete coverage, while switching off the rest. In this paper, we ...
Arijit Ghosh, Tony Givargis
DATE
2005
IEEE
143views Hardware» more  DATE 2005»
8 years 7 months ago
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the...
Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay,...
DATE
2005
IEEE
131views Hardware» more  DATE 2005»
8 years 7 months ago
Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions
— We propose a sensitivity-based method to allocate decaps incorporating leakage constraints and tighter data and clock interactions. The proposed approach attempts to allocate d...
Ajith Chandy, Tom Chen
DATE
2005
IEEE
100views Hardware» more  DATE 2005»
8 years 7 months ago
The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application
Developing a functional prototype of a system-on-chip provides a unifying vehicle for model validation and system refinement. Keeping the prototype executable everal abstraction l...
Alexandre Chureau, Yvon Savaria, El Mostapha Aboul...
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