Sciweavers

DATE
2005
IEEE
93views Hardware» more  DATE 2005»
13 years 9 months ago
Model Reuse through Hardware Design Patterns
Increasing reuse opportunities is a well-known problem for software designers as well as for hardware designers. Nonetheless, current software and hardware engineering practices h...
Fernando Rincón, Francisco Moya, Jesú...
DATE
2005
IEEE
104views Hardware» more  DATE 2005»
13 years 9 months ago
A SoC Design Methodology Involving a UML 2.0 Profile for SystemC
In this paper, we present a SoC design methodology joining the capabilities of UML and SystemC to operate at systemlevel. We present a UML 2.0 profile of the SystemC language expl...
Elvinia Riccobene, Patrizia Scandurra, Alberto Ros...
DATE
2005
IEEE
102views Hardware» more  DATE 2005»
13 years 9 months ago
Lifetime Modeling of a Sensor Network
Vivek Rai, Rabi N. Mahapatra
DATE
2005
IEEE
116views Hardware» more  DATE 2005»
13 years 9 months ago
FPGA based Agile Algorithm-On-Demand Co-Processor
With growing computational needs of many real-world applications, frequently changing specifications of standards, and the high design and NRE costs of ASICs, an algorithm-agile ...
Ramachandran Pradeep, S. Vinay, Sanjay Burman, V. ...
DATE
2005
IEEE
126views Hardware» more  DATE 2005»
13 years 9 months ago
The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits
We investigate a new fault ordering heuristic for test generation in full-scan circuits. The heuristic is referred to as the accidental detection index. It associates a value ADI ...
Irith Pomeranz, Sudhakar M. Reddy
DATE
2005
IEEE
99views Hardware» more  DATE 2005»
13 years 9 months ago
Worst-Case and Average-Case Analysis of n-Detection Test Sets
Test sets that detect each target fault n times (n-detection test sets) are typically generated for restricted values of n due to the increase in test set size with n. We perform ...
Irith Pomeranz, Sudhakar M. Reddy
DATE
2005
IEEE
172views Hardware» more  DATE 2005»
13 years 9 months ago
Evolutionary Optimization in Code-Based Test Compression
We provide a general formulation for the code-based test compression problem with fixed-length input blocks and propose a solution approach based on Evolutionary Algorithms. In c...
Ilia Polian, Alejandro Czutro, Bernd Becker
DATE
2005
IEEE
104views Hardware» more  DATE 2005»
13 years 9 months ago
Queue Management in Network Processors
: - One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at...
Ioannis Papaefstathiou, Theofanis Orphanoudakis, G...
DATE
2005
IEEE
171views Hardware» more  DATE 2005»
13 years 9 months ago
Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems
As compared to a large spectrum of performance optimizations, relatively little effort has been dedicated to optimize other aspects of embedded applications such as memory space r...
Ozcan Ozturk, Hendra Saputra, Mahmut T. Kandemir, ...