Sciweavers

DATE
2006
IEEE
64views Hardware» more  DATE 2006»
13 years 10 months ago
Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
DATE
2006
IEEE
86views Hardware» more  DATE 2006»
13 years 10 months ago
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips
Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinis...
DATE
2006
IEEE
108views Hardware» more  DATE 2006»
13 years 10 months ago
Architectural and technology influence on the optimal total power consumption
In this paper, an approximated closed-form total power consumption equation for circuits working at their optimal supply and threshold voltage is presented. Comparisons of this fo...
Christian Schuster, Jean-Luc Nagel, Christian Pigu...
DATE
2006
IEEE
90views Hardware» more  DATE 2006»
13 years 10 months ago
A time predictable Java processor
This paper presents a Java processor, called JOP, designed for time-predictable execution of real-time tasks. JOP is the implementation of the Java virtual machine in hardware. We...
Martin Schoeberl
DATE
2006
IEEE
147views Hardware» more  DATE 2006»
13 years 10 months ago
Quantitative analysis of transaction level models for the AMBA bus
The increasing complexity of embedded systems pushes system designers to higher levels of abstraction. Transaction Level Modeling (TLM) has been proposed to model ation in systems...
Gunar Schirner, Rainer Dömer
DATE
2006
IEEE
101views Hardware» more  DATE 2006»
13 years 10 months ago
Design with race-free hardware semantics
Most hardware description languages do not enforce determinacy, meaning that they may yield races. Race conditions pose a problem for the implementation, verification, and validat...
Patrick Schaumont, Sandeep K. Shukla, Ingrid Verba...
DATE
2006
IEEE
113views Hardware» more  DATE 2006»
13 years 10 months ago
An interprocedural code optimization technique for network processors using hardware multi-threading support
Sophisticated C compiler support for network processors (NPUs) is required to improve their usability and consequently, their acceptance in system design. Nonetheless, high-level ...
Hanno Scharwächter, Manuel Hohenauer, Rainer ...
DATE
2006
IEEE
142views Hardware» more  DATE 2006»
13 years 10 months ago
Mixed-signal design of a digital input power amplifier for automotive audio applications
With reference to digital input power amplifier for automotive audio applications, the paper presents an exhaustive exploration of the huge mixed-signal space to find optimal trad...
Sergio Saponara, Pierangelo Terreni
DATE
2006
IEEE
173views Hardware» more  DATE 2006»
13 years 10 months ago
3dID: a low-power, low-cost hand motion capture device
This paper presents a novel input device design for capturing gestures. The system is based on commodity components and combines accelerometers, gyroscopes and bend sensors. It is...
Michele Sama, Vincenzo Pacella, Elisabetta Farella...
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
13 years 10 months ago
Pre-synthesis optimization of multiplications to improve circuit performance
Conventional high-level synthesis uses the worst case delay to relate all inputs to all outputs of an operation. This is a very conservative approximation of reality, especially i...
Rafael Ruiz-Sautua, María C. Molina, Jos&ea...