Sciweavers

DATE
2007
IEEE
105views Hardware» more  DATE 2007»
13 years 10 months ago
A tiny and efficient wireless ad-hoc protocol for low-cost sensor networks
Pawel Gburzynski, Bozena Kaminska, Wladek Olesinsk...
DATE
2007
IEEE
154views Hardware» more  DATE 2007»
13 years 10 months ago
Soft error rate analysis for sequential circuits
Due to reduction in device feature size and supply voltage, the sensitivity to radiation induced transient faults (soft errors) of digital systems increases dramatically. Intensiv...
Natasa Miskov-Zivanov, Diana Marculescu
DATE
2007
IEEE
155views Hardware» more  DATE 2007»
13 years 10 months ago
Design fault directed test generation for microprocessor validation
Functional validation of modern microprocessors is an important and complex problem. One of the problems in functional validation is the generation of test cases that has higher p...
Deepak Mathaikutty, Sandeep K. Shukla, Sreekumar V...
DATE
2007
IEEE
118views Hardware» more  DATE 2007»
13 years 10 months ago
An area optimized reconfigurable encryptor for AES-Rijndael
Monjur Alam, Sonai Ray, Debdeep Mukhopadhyay, Sant...
DATE
2007
IEEE
127views Hardware» more  DATE 2007»
13 years 10 months ago
A calculator for Pareto points
This paper presents the Pareto Calculator, a tool for compositional computation of Pareto points, based on the algebra of Pareto points. The tool is a useful instrument for multidi...
Marc Geilen, Twan Basten
DATE
2007
IEEE
109views Hardware» more  DATE 2007»
13 years 10 months ago
Area optimization of multi-cycle operators in high-level synthesis
Conventional high-level synthesis algorithms usually employ multi-cycle operators to reduce the cycle length in order to improve the circuit performance. These operators need seve...
María C. Molina, Rafael Ruiz-Sautua, Jose M...
DATE
2007
IEEE
74views Hardware» more  DATE 2007»
13 years 10 months ago
Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks
High reliability against noise, low energy consumption and high performance are key objectives in the design of on-chip networks. Recently some researchers have considered the var...
Alireza Ejlali, Bashir M. Al-Hashimi, Paul M. Rosi...
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
13 years 10 months ago
Assessing carbon nanotube bundle interconnect for future FPGA architectures
Field Programmable Gate Arrays (FPGAs) are important hardware platforms in various applications due to increasing design complexity and mask costs. However, as CMOS process techno...
Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen,...
DATE
2007
IEEE
84views Hardware» more  DATE 2007»
13 years 10 months ago
On test generation by input cube avoidance
Test generation procedures attempt to assign values to the inputs of a circuit so as to detect target faults. We study a complementary view whereby the goal is to identify values ...
Irith Pomeranz, Sudhakar M. Reddy
DATE
2007
IEEE
86views Hardware» more  DATE 2007»
13 years 10 months ago
Thermally robust clocking schemes for 3D integrated circuits
3D integration of multiple active layers into a single chip is a viable technique that greatly reduces the length of global wires by providing vertical connections between layers....
Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Ta...