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DATE
2008
IEEE
124views Hardware» more  DATE 2008»
13 years 10 months ago
Resistive Bridging Fault Simulation of Industrial Circuits
We report the successful application of a resistive bridging fault (RBF) simulator to industrial benchmark circuits. Despite the slowdown due to the consideration of the sophistic...
Piet Engelke, Ilia Polian, Jürgen Schlöf...
DATE
2008
IEEE
106views Hardware» more  DATE 2008»
13 years 10 months ago
Software Components for Reliable Automotive Systems
System-level integration requires an overall understanding of the interplay of the sub-systems to enable componentbased development with portability, reconfigurability and extens...
Harald Heinecke, Werner Damm, Bernhard Josko, Alex...
DATE
2008
IEEE
62views Hardware» more  DATE 2008»
13 years 10 months ago
Instruction Cache Energy Saving Through Compiler Way-Placement
Fetching instructions from a set-associative cache in an embedded processor can consume a large amount of energy due to the tag checks performed. Recent proposals to address this ...
Timothy M. Jones, Sandro Bartolini, Bruno De Bus, ...
DATE
2008
IEEE
101views Hardware» more  DATE 2008»
13 years 10 months ago
A Game-Theoretic Approach to Real-Time System Testing
This paper presents a game-theoretic approach to the testing of uncontrollable real-time systems. By modelling the systems with Timed I/O Game Automata and specifying the test pur...
Alexandre David, Kim Guldstrand Larsen, Shuhao Li,...
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
13 years 10 months ago
A Single-supply True Voltage Level Shifter
When a signal traverses on-chip voltage domains, a level shifter is required. Inverters can handle a high to low voltage shift with minimal leakage. For a low to high voltage leve...
Rajesh Garg, Gagandeep Mallarapu, Sunil P. Khatri
DATE
2008
IEEE
117views Hardware» more  DATE 2008»
13 years 10 months ago
A Scalable Algorithmic Framework for Row-Based Power-Gating
Leakage power is a serious concern in nanometer CMOS technologies. In this paper we focus on leakage reduction through automatic insertion of sleep transistors for power gating in...
Ashoka Visweswara Sathanur, Antonio Pullini, Luca ...
DATE
2008
IEEE
86views Hardware» more  DATE 2008»
13 years 10 months ago
Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs
Abstract—Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testi...
Sudarshan Bahukudumbi, Krishnendu Chakrabarty, Ric...
DATE
2008
IEEE
107views Hardware» more  DATE 2008»
13 years 10 months ago
Merged Computation for Whirlpool Hashing
This paper presents an improved hardware structure for the computation of the Whirlpool hash function. By merging the round key computation with the data compression and by using ...
Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Sta...
DATE
2008
IEEE
149views Hardware» more  DATE 2008»
13 years 10 months ago
OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks
Accurate power and performance figures are critical to assess the effective design of possible sensor node architectures in Body Area Networks (BANs) since they operate on limite...
Francisco J. Rincón, Michele Paselli, Joaqu...