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DATE
2009
IEEE
171views Hardware» more  DATE 2009»
9 years 7 months ago
Physically clustered forward body biasing for variability compensation in nanometer CMOS design
Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse consequences on design predictability and yield. A number of recent works have...
Ashoka Visweswara Sathanur, Antonio Pullini, Luca ...
DATE
2009
IEEE
88views Hardware» more  DATE 2009»
9 years 7 months ago
A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment
Growing test data volume and overtesting caused by excessive scan capture power are two of the major concerns for the industry when testing large integrated circuits. Various test...
Xiao Liu, Qiang Xu
DATE
2009
IEEE
138views Hardware» more  DATE 2009»
9 years 7 months ago
An approximation scheme for energy-efficient scheduling of real-time tasks in heterogeneous multiprocessor systems
As application complexity increases, modern embedded systems have adopted heterogeneous processing elements to enhance the computing capability or to reduce the power consumption. ...
Chuan-Yue Yang, Jian-Jia Chen, Tei-Wei Kuo, Lothar...
DATE
2009
IEEE
99views Hardware» more  DATE 2009»
9 years 7 months ago
Detecting errors using multi-cycle invariance information
Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris...
DATE
2009
IEEE
91views Hardware» more  DATE 2009»
9 years 7 months ago
Optimizing the HW/SW boundary of an ECC SoC design using control hierarchy and distributed storage
Abstract--Hardware/Software codesign of Elliptic Curve Cryptography has been extensively studied in recent years. However, most of these designs have focused on the computational a...
Xu Guo, Patrick Schaumont
DATE
2009
IEEE
115views Hardware» more  DATE 2009»
9 years 7 months ago
Customizing IP cores for system-on-chip designs using extensive external don't-cares
Traditional digital circuit synthesis flows start from an HDL behavioral definition and assume that circuit functions are almost completely defined, making don't-care conditio...
Kai-Hui Chang, Valeria Bertacco, Igor L. Markov
DATE
2009
IEEE
64views Hardware» more  DATE 2009»
9 years 7 months ago
Speculative reduction-based scalable redundancy identification
The process of sequential redundancy identification is the cornerstone of sequential synthesis and equivalence checking frameworks. The scalability of the proof obligations inhere...
Hari Mony, Jason Baumgartner, Alan Mishchenko, Rob...
DATE
2009
IEEE
118views Hardware» more  DATE 2009»
9 years 7 months ago
Variation resilient adaptive controller for subthreshold circuits
Subthreshold logic is showing good promise as a viable ultra-low-power circuit design technique for powerlimited applications. For this design technique to gain widespread adoption...
Biswajit Mishra, Bashir M. Al-Hashimi, Mark Zwolin...
DATE
2009
IEEE
123views Hardware» more  DATE 2009»
9 years 7 months ago
Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis
This paper exploits the unique in-field controllability of the device polarity of ambipolar carbon nanotube field effect transistors (CNTFETs) to design a technology library with ...
M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De ...
DATE
2009
IEEE
120views Hardware» more  DATE 2009»
9 years 10 months ago
Optimizing data flow graphs to minimize hardware implementation
Abstract - This paper describes an efficient graphbased method to optimize data-flow expressions for best hardware implementation. The method is based on factorization, common su...
Daniel Gomez-Prado, Q. Ren, Maciej J. Ciesielski, ...
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