Sciweavers

DATE
2009
IEEE
128views Hardware» more  DATE 2009»
13 years 11 months ago
Configurable links for runtime adaptive on-chip communication
Mohammad Abdullah Al Faruque, Thomas Ebi, Jör...
DATE
2009
IEEE
138views Hardware» more  DATE 2009»
13 years 11 months ago
Hardware/software co-design architecture for thermal management of chip multiprocessors
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
Omer Khan, Sandip Kundu
DATE
2009
IEEE
85views Hardware» more  DATE 2009»
13 years 11 months ago
SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems
- Parallel architectures have become an increasingly popular method in which to achieve high performance with low power consumption. In order to leverage these benefits, applicatio...
Abelardo Jara-Berrocal, Ann Gordon-Ross
DATE
2009
IEEE
111views Hardware» more  DATE 2009»
13 years 11 months ago
Increased accuracy through noise injection in abstract RTOS simulation
RTOS Simulation Henning Zabel, Wolfgang Mueller Universität Paderborn, C-LAB Fürstenallee 11, D-33102 Paderborn, Germany —Today, mobile and embedded real-time systems have to c...
Henning Zabel, Wolfgang Mueller
DATE
2009
IEEE
112views Hardware» more  DATE 2009»
13 years 11 months ago
Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design
—Due to increasing complexity of design interactions between the chip, package and PCB, it is essential to consider them at the same time. Specifically the finger/pad locations...
Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu,...
DATE
2009
IEEE
248views Hardware» more  DATE 2009»
13 years 11 months ago
KAST: K-associative sector translation for NAND flash memory in real-time systems
Abstract—Flash memory is a good candidate for the storage device in real-time systems due to its non-fluctuating performance, low power consumption and high shock resistance. Ho...
Hyun-jin Cho, Dongkun Shin, Young Ik Eom
DATE
2009
IEEE
148views Hardware» more  DATE 2009»
13 years 11 months ago
A new design-for-test technique for SRAM core-cell stability faults
—Core-cell stability represents the ability of the core-cell to keep the stored data. With the rapid development of semiconductor memories, their test is becoming a major concern...
Alexandre Ney, Luigi Dilillo, Patrick Girard, Serg...
DATE
2009
IEEE
134views Hardware» more  DATE 2009»
13 years 11 months ago
Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures
We address the problem of real-time streaming applications scheduling on hybrid CPU/FPGA architectures. The main contribution is a two-step approach to minimize the buffer require...
Jun Zhu, Ingo Sander, Axel Jantsch
DATE
2009
IEEE
78views Hardware» more  DATE 2009»
13 years 11 months ago
QC-Fill: An X-Fill method for quick-and-cool scan test
— In this paper, we present an X-Fill (QC-Fill) method for not only slashing the test time but also reducing the test power (including both capture power and shifting power). QC-...
Chao-Wen Tzeng, Shi-Yu Huang