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DATE
2009
IEEE
103views Hardware» more  DATE 2009»
9 years 10 months ago
A set-based mapping strategy for flash-memory reliability enhancement
—With wide applicability of flash memory in various application domains, reliability has become a very critical issue. This research is motivated by the needs to resolve the lif...
Yuan-Sheng Chu, Jen-Wei Hsieh, Yuan-Hao Chang, Tei...
DATE
2009
IEEE
126views Hardware» more  DATE 2009»
9 years 10 months ago
Fast and accurate protocol specific bus modeling using TLM 2.0
—The need to have Transaction Level models early in the design cycle is becoming more and more important to shorten the development times of complex Systems-on-Chip (SoC). These ...
H. W. M. van Moll, Henk Corporaal, Víctor R...
DATE
2009
IEEE
146views Hardware» more  DATE 2009»
9 years 10 months ago
Heterogeneous multi-core platform for consumer multimedia applications
—This paper presents a multi-core SoC architecture for consumer multimedia applications. The comprehensive functionality of such multimedia systems is described using the example...
Peter Kollig, Colin Osborne, Tomas Henriksson
DATE
2009
IEEE
135views Hardware» more  DATE 2009»
9 years 10 months ago
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration
Reconfigurable Architectures are good candidates for application accelerators that cannot be set in stone at production time. FPGAs however, often suffer from the area and perfor...
Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
DATE
2009
IEEE
194views Hardware» more  DATE 2009»
9 years 10 months ago
A UML frontend for IP-XACT-based IP management
—IP-XACT is a well accepted standard for the exchange of IP components at Electronic System and Register Transfer Level. Still, the creation and manipulation of these description...
Tim Schattkowsky, Tao Xie, Wolfgang Mueller
DATE
2009
IEEE
116views Hardware» more  DATE 2009»
9 years 10 months ago
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints
In this paper, we propose a preprocessing method to improve Side Channel Attacks (SCAs) on Dual-rail with Precharge Logic (DPL) countermeasure family. The strength of our method i...
Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger,...
DATE
2009
IEEE
93views Hardware» more  DATE 2009»
9 years 10 months ago
Scalable liveness checking via property-preserving transformations
The ability of logic transformations to enhance safety property checking has been well-established, and many industrial-strength verification solutions accordingly rely ariety of...
Jason Baumgartner, Hari Mony
DATE
2009
IEEE
98views Hardware» more  DATE 2009»
9 years 10 months ago
Dynamic and distributed frequency assignment for energy and latency constrained MP-SoC
—In this paper we present an adaptive technique to locally adjust the frequency of processing elements on MP-SoC. The proposed method, based on Game Theory, optimizes the system ...
Diego Puschini, Fabien Clermidy, Pascal Benoit, Gi...
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