Sciweavers

DATE
2009
IEEE
86views Hardware» more  DATE 2009»
13 years 10 months ago
A power-efficient migration mechanism for D-NUCA caches
D-NUCA L2 caches are able to tolerate the increasing wire delay effects due to technology scaling thanks to their banked organization, broadcast line search and data promotion/dem...
Alessandro Bardine, Manuel Comparetti, Pierfrances...
DATE
2009
IEEE
122views Hardware» more  DATE 2009»
13 years 10 months ago
MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues
—Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced i...
Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuy...
DATE
2009
IEEE
101views Hardware» more  DATE 2009»
13 years 10 months ago
Speeding up model checking by exploiting explicit and hidden verification constraints
Gianpiero Cabodi, Paolo Camurati, Luz Garcia, Marc...
DATE
2009
IEEE
90views Hardware» more  DATE 2009»
13 years 10 months ago
A scalable method for the generation of small test sets
This paper presents a scalable method to generate close to minimal size test pattern sets for stuck-at faults in scan based circuits. The method creates sets of potentially compat...
Santiago Remersaro, Janusz Rajski, Sudhakar M. Red...
DATE
2009
IEEE
87views Hardware» more  DATE 2009»
13 years 10 months ago
Efficient compression and handling of current source model library waveforms
—This paper describes a waveform compression technique suitable for the efficient utilization, storage and interchange of the emerging current source model (CSM) based cell libra...
Safar Hatami, Peter Feldmann, Soroush Abbaspour, M...
DATE
2009
IEEE
141views Hardware» more  DATE 2009»
13 years 10 months ago
Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis
– The quest for technologies with superior device characteristics has showcased Carbon Nanotube Field Effect Transistors (CNFETs) into limelight. Among the several design aspects...
Shashikanth Bobba, Jie Zhang, Antonio Pullini, Dav...
DATE
2009
IEEE
113views Hardware» more  DATE 2009»
13 years 10 months ago
System-level process variability analysis and mitigation for 3D MPSoCs
Abstract—While prior research has extensively evaluated the performance advantage of moving from a 2D to a 3D design style, the impact of process parameter variations on 3D desig...
Siddharth Garg, Diana Marculescu
DATE
2009
IEEE
112views Hardware» more  DATE 2009»
13 years 10 months ago
Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesis
: Common sub-expression elimination (CSE) serves as a useful optimization technique in the synthesis of arithmetic datapaths described at RTL. However, CSE has a limited potential ...
Sivaram Gopalakrishnan, Priyank Kalla
DATE
2009
IEEE
110views Hardware» more  DATE 2009»
13 years 10 months ago
Error correction in single-hop wireless sensor networks - A case study
—Energy efficient communication is a key issue in wireless sensor networks. Common belief is that a multi-hop configuration is the only viable energy efficient technique. In t...
Daniel Schmidt 0001, Matthias Berning, Norbert Weh...