Sciweavers

DDECS
2006
IEEE
83views Hardware» more  DDECS 2006»
13 years 8 months ago
Embedded Self Repair by Transistor and Gate Level Reconfiguration
René Kothe, Heinrich Theodor Vierhaus, Tors...
DDECS
2006
IEEE
140views Hardware» more  DDECS 2006»
13 years 8 months ago
A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming
Abstract-- Genetic Parallel Programming (GPP) evolves parallel programs for MIMD architectures with multiple arithmetic/logic processors (MAPs). This paper describes a tool intende...
Zbysek Gajda
DDECS
2006
IEEE
146views Hardware» more  DDECS 2006»
13 years 8 months ago
Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis
Abstract-- Hard real-time systems need methods to determine upper bounds for their execution times, usually called worst-case execution times. Timing anomalies are counterintuitive...
Jochen Eisinger, Ilia Polian, Bernd Becker, Alexan...
DDECS
2006
IEEE
101views Hardware» more  DDECS 2006»
13 years 10 months ago
Embedded Built-In-Test Detection Circuit for Radio Frequency Systems and Circuits
: An embedded rectifier-based Built-In-Test (BIT) detection circuit for the RF integrated circuits is proposed in this work, and charge pump rectifier is adopted to transform the R...
Guoyan Zhang, Ronan Farrell
DDECS
2006
IEEE
106views Hardware» more  DDECS 2006»
13 years 10 months ago
Dynamic Decimal Adder Circuit Design by using the Carry Lookahead
- This paper presents a carry lookahead (CLA) circuitry design based on dynamic circuit aiming at delay reduction in addition of BCD coded decimal numbers. The performance of the p...
Younggap You, Yong-Dae Kim, Jong Hwa Choi
DDECS
2006
IEEE
108views Hardware» more  DDECS 2006»
13 years 10 months ago
Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder
—The impact of shared instruction memory on performance is measured and analyzed for an FPGAbased Multiprocessor System-on-Chip (MP-SoC) with an MPEG-4 video encoding application...
Ari Kulmala, Erno Salminen, Olli Lehtoranta, Timo ...
DDECS
2006
IEEE
88views Hardware» more  DDECS 2006»
13 years 10 months ago
Minimization of Large State Spaces using Symbolic Branching Bisimulation
Abstract: Bisimulations in general are a powerful concept to minimize large finite state systems regarding some well-defined observational behavior. In contrast to strong bisimul...
Ralf Wimmer, Marc Herbstritt, Bernd Becker
DDECS
2006
IEEE
79views Hardware» more  DDECS 2006»
13 years 10 months ago
Multiple-Vector Column-Matching BIST Design Method
- Extension of a BIST design algorithm is proposed in this paper. The method is based on a synthesis of a combinational block - the decoder, transforming pseudo-random code words i...
Petr Fiser, Hana Kubatova
DDECS
2006
IEEE
94views Hardware» more  DDECS 2006»
13 years 10 months ago
A System for Transforming an ANSI C Code with OpenMP Directives into a SystemC Description
Abstract— In this paper, we describe a system for transforming a code given in ANSI C into an equivalent SystemC description. In order to synthesize parallel C codes into hardwar...
Piotr Dziurzanski, W. Bielecki, Konrad Trifunovic,...