DDECS
2009
IEEE
13 years 5 months ago
2009
IEEE
High-speed (10 Gb/s and above) network monitoring and traffic processing requires hardware acceleration. Different applications require different functions to be placed in hardware...
DDECS
2009
IEEE
13 years 8 months ago
2009
IEEE
DDECS
2009
IEEE
13 years 8 months ago
2009
IEEE
DDECS
2009
IEEE
13 years 8 months ago
2009
IEEE
Low power consumption and high-performance are two main directions in the development of modern microprocessor architectures. In general they are two excluding branches of System-o...
DDECS
2009
IEEE
13 years 8 months ago
2009
IEEE
Although the Neighborhood Pattern Sensitive Fault (NPSF) model is recognized as a high quality fault model for memory arrays, the excessive test application time cost associated wi...
DDECS
2009
IEEE
13 years 11 months ago
2009
IEEE
—Self-timed full adder designs based on commercial synchronous resources (standard cells), constructed using a mix of complete delay-insensitive codes adopted for inputs are desc...
DDECS
2009
IEEE
13 years 11 months ago
2009
IEEE
— We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints....
DDECS
2009
IEEE
13 years 11 months ago
2009
IEEE
—Automatic Test Pattern Generation (ATPG) based on Boolean satisfiability (SAT) has been shown to be a beneficial complement to traditional ATPG techniques. Boolean solvers wor...
DDECS
2009
IEEE
13 years 11 months ago
2009
IEEE
– A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and...
DDECS
2009
IEEE
13 years 11 months ago
2009
IEEE
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...