Sciweavers

CDES
2006

158views Hardware» more CDES 2006»

A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs

13 years 6 months ago

In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...

Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia

claim paper

Read More »

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers