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    DAC
    1998
    ACM
    137views Computer Architecture» more  DAC 1998»
    Layout Techniques for Minimizing On-Chip Interconnect Self Inductance
    14 years 5 months ago
    Layout Techniques for Minimizing On-Chip Interconnect Self Inductance
    Download  www.rle.mit.edu
    Because magnetic e ects have a much longer spatial range than electrostatic e ects, an interconnect line with large inductance will be sensitive to distant variations in interconn...
    Yehia Massoud, Steve S. Majors, Tareq Bustami, Jac...
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