Sciweavers

Share
DAC
1994
ACM
9 years 5 months ago
Clock Grouping: A Low Cost DFT Methodology for Delay Testing
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
Wen-Chang Fang, Sandeep K. Gupta
IOLTS
2000
IEEE
105views Hardware» more  IOLTS 2000»
9 years 6 months ago
Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
Patrick Girard, Christian Landrault, Serge Pravoss...
books