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ETS
2009
IEEE
98views Hardware» more  ETS 2009»
8 years 3 months ago
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques
Due to the increased speed in modern designs, testing for delay faults has become an important issue in the postproduction test of manufactured chips. A high fault coverage is nee...
Stephan Eggersglüß, Rolf Drechsler
JISE
2000
68views more  JISE 2000»
8 years 5 months ago
Testable Path Delay Fault Cover for Sequential Circuits
We present an algorithm for identifyinga set of faults that do not have to be targeted by a sequential delay fault test generator. These faults either cannot independently aect th...
Angela Krstic, Srimat T. Chakradhar, Kwang-Ting Ch...
ASPDAC
2005
ACM
107views Hardware» more  ASPDAC 2005»
8 years 7 months ago
Constraint extraction for pseudo-functional scan-based delay testing
Recent research results have shown that the traditional structural testing for delay and crosstalk faults may result in over-testing due to the non-trivial number of such faults t...
Yung-Chieh Lin, Feng Lu, Kai Yang, Kwang-Ting Chen...
ASPDAC
2005
ACM
96views Hardware» more  ASPDAC 2005»
8 years 7 months ago
Oscillation ring based interconnect test scheme for SOC
- We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and cr...
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, ...
ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
8 years 9 months ago
Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes
- Two methods to apply tests to detect delay faults in standard scan designs are used. One is called launch off capture and the other is called launch off shift. Launch off shift t...
Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz
DAC
1994
ACM
8 years 9 months ago
Clock Grouping: A Low Cost DFT Methodology for Delay Testing
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
Wen-Chang Fang, Sandeep K. Gupta
ITC
1996
IEEE
83views Hardware» more  ITC 1996»
8 years 9 months ago
Test Generation for Global Delay Faults
This paper describes test generation for delay faults caused by global process disturbances. The structural and spatial correlation between path delays is used to reduce the numbe...
G. M. Luong, D. M. H. Walker
DATE
1997
IEEE
100views Hardware» more  DATE 1997»
8 years 9 months ago
On the generation of pseudo-deterministic two-patterns test sequence with LFSRs
Many Built-In Self Test pattern generators use Linear Feedback Shift Registers (LFSR) to generate test sequences. In this paper, we address the generation of deterministic pairs o...
Christian Dufaza, Yervant Zorian
VTS
1999
IEEE
108views Hardware» more  VTS 1999»
8 years 9 months ago
Adaptive Techniques for Improving Delay Fault Diagnosis
This paper presents adaptive techniques for improving delay fault diagnosis. These techniques reduce the search space for direct probing which can save a lot of time during failur...
Jayabrata Ghosh-Dastidar, Nur A. Touba
DATE
2010
IEEE
134views Hardware» more  DATE 2010»
8 years 10 months ago
Layout-aware pseudo-functional testing for critical paths considering power supply noise effects
When testing delay faults on critical paths, conventional structural test patterns may be applied in functionally-unreachable states, leading to over-testing or under-testing of t...
Xiao Liu, Yubin Zhang, Feng Yuan, Qiang Xu
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