SODA
2003
ACM
13 years 5 months ago
2003
ACM
We consider packet scheduling in a network providing differentiated services, where each packet is assigned a value. We study various queueing models for supporting QoS (Quality ...
DAC
2005
ACM
13 years 6 months ago
2005
ACM
We present an efficient and accurate gate sizing tool that employs a novel piecewise convex delay model, handling both rise and fall delays, for static CMOS gates. The delay model...
ICCAD
1994
IEEE
13 years 8 months ago
1994
IEEE
We give the rst single-layer clock tree construction with exact zero skew according to the Elmore delay model. The previous Linear-Planar-DME method 11 guarantees a planar solutio...
ICCAD
1997
IEEE
13 years 8 months ago
1997
IEEE
This paper is concerned with approximate delay computation algorithms for combinational circuits. As a result of intensive research in the early 90’s [3, 8] efficient tools exi...
DATE
1998
IEEE
13 years 8 months ago
1998
IEEE
Despite its importance, we find that a rigorous theoretical foundation for performing timing analysis has been lacking so far. As a result, we have initiated a research project th...
VLSID
1999
IEEE
13 years 8 months ago
1999
IEEE
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
ICCAD
1999
IEEE
13 years 8 months ago
1999
IEEE
Typically,cell parameterssuch as the pin-to-pinintrinsicdelays, load-dependentcoe cients,andinputpin capacitanceshavedifferent values for rising and falling signals. The performan...
ICCAD
2000
IEEE
13 years 8 months ago
2000
IEEE
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...
ISQED
2003
IEEE
13 years 9 months ago
2003
IEEE
In this paper we propose a new design methodology targeted for core-based designs using parameterized macrocells (PMC’s). This methodology provides the flexibility for instance...
ANSS
2003
IEEE
13 years 9 months ago
2003
IEEE
In this work, we present a computational behavioral model for logic gates called Internode (Internal Node Logic Computational Model) that considers the functionality of the gate a...