ITC
1993
IEEE
13 years 8 months ago
1993
IEEE
This paper presents an efficient approach to generate tests for gate delay faults. Unlike other known algorithms which try to generate a 'good' delay test the presented ...
VLSID
1996
IEEE
13 years 8 months ago
1996
IEEE
W epropose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and ...
ISQED
2003
IEEE
13 years 9 months ago
2003
IEEE
A structurally testable delay fault might become untestable in the functional mode of the circuit due to logic or timing constraints or both. Experimental data suggests that there...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
This paper presents a case-study of delay defect screening applied to Fujitsu 2.16GHz SPARC64 microprocessor. A nonrobust delay test is used while each test vector is compacted to...
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
We present an approach to prevent overtesting in scan-based delay test. The test data is transformed with respect to functional constraints while simultaneously keeping as many po...
VTS
2007
IEEE
13 years 10 months ago
2007
IEEE
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...
DAC
2004
ACM
14 years 5 months ago
2004
ACM