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DATE
2008
IEEE
145views Hardware» more  DATE 2008»
9 years 2 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
CODES
2008
IEEE
9 years 2 months ago
Static analysis for fast and accurate design space exploration of caches
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in partic...
Yun Liang, Tulika Mitra
CEC
2008
IEEE
9 years 2 months ago
High-level synthesis with multi-objective genetic algorithm: A comparative encoding analysis
— The high-level synthesis process involves three interdependent and NP-complete optimization problems: (i) the operation scheduling, (ii) the resource allocation, and (iii) the ...
Christian Pilato, Daniele Loiacono, Fabrizio Ferra...
ASPDAC
2009
ACM
110views Hardware» more  ASPDAC 2009»
9 years 2 months ago
Variability-aware robust design space exploration of chip multiprocessor architectures
Abstract— In the context of a design space exploration framework for supporting the platform-based design approach, we address the problem of robustness with respect to manufactu...
Gianluca Palermo, Cristina Silvano, Vittorio Zacca...
ESTIMEDIA
2009
Springer
9 years 2 months ago
System-level MP-SoC design space exploration using tree visualization
— The complexity of today’s embedded systems forces designers to model and simulate systems and their components to explore the wide range of design choices. Such design space ...
Toktam Taghavi, Andy D. Pimentel, Mark Thompson
DATE
2009
IEEE
105views Hardware» more  DATE 2009»
9 years 3 months ago
UMTS MPSoC design evaluation using a system level design framework
Rapid design space exploration with accurate models is necessary to improve designer productivity at the electronic system level. We describe how to use a new event-based design f...
Douglas Densmore, Alena Simalatsar, Abhijit Davare...
DATE
2009
IEEE
86views Hardware» more  DATE 2009»
9 years 3 months ago
A formal approach to design space exploration of protocol converters
In the field of chip design, hardware module reuse is a standard solution to the increasing complexity of chip architecture and the pressures to reduce time to market. In the abs...
Karin Avnit, Arcot Sowmya
ICCD
2000
IEEE
135views Hardware» more  ICCD 2000»
9 years 5 months ago
A Methodology and Tool for Automated Transformational High-Level Design Space Exploration
el of abstraction by integrating a high-level estimation step. This results in a design loop which is tight led on high level of abstraction (called estimation loop in figure 1). ...
Joachim Gerlach, Wolfgang Rosenstiel
ICCD
2006
IEEE
118views Hardware» more  ICCD 2006»
9 years 5 months ago
A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models
—This paper presents a system-level Network-on-Chip modeling framework that integrates transaction-level model and analytical wire model for design space exploration. It enables ...
Jinwen Xi, Peixin Zhong
DAC
2006
ACM
9 years 9 months ago
Design space exploration using time and resource duality with the ant colony optimization
Design space exploration during high level synthesis is often conducted through ad-hoc probing of the solution space using some scheduling algorithm. This is not only time consumi...
Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastne...
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