DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
CODES
2008
IEEE
13 years 11 months ago
2008
IEEE
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in partic...
CEC
2008
IEEE
13 years 11 months ago
2008
IEEE
— The high-level synthesis process involves three interdependent and NP-complete optimization problems: (i) the operation scheduling, (ii) the resource allocation, and (iii) the ...
ASPDAC
2009
ACM
13 years 11 months ago
2009
ACM
Abstract— In the context of a design space exploration framework for supporting the platform-based design approach, we address the problem of robustness with respect to manufactu...
ESTIMEDIA
2009
Springer
13 years 11 months ago
2009
Springer
— The complexity of today’s embedded systems forces designers to model and simulate systems and their components to explore the wide range of design choices. Such design space ...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
Rapid design space exploration with accurate models is necessary to improve designer productivity at the electronic system level. We describe how to use a new event-based design f...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
In the field of chip design, hardware module reuse is a standard solution to the increasing complexity of chip architecture and the pressures to reduce time to market. In the abs...
ICCD
2000
IEEE
14 years 1 months ago
2000
IEEE
el of abstraction by integrating a high-level estimation step. This results in a design loop which is tight led on high level of abstraction (called estimation loop in figure 1). ...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
—This paper presents a system-level Network-on-Chip modeling framework that integrates transaction-level model and analytical wire model for design space exploration. It enables ...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
Design space exploration during high level synthesis is often conducted through ad-hoc probing of the solution space using some scheduling algorithm. This is not only time consumi...