Sciweavers

GLVLSI
2010
IEEE
210views VLSI» more  GLVLSI 2010»
13 years 9 months ago
Overscaling-friendly timing speculation architectures
Processors have traditionally been designed for the worst-case, resulting in designs that have high yields, but are expensive in terms of area and power. Better-than-worst-case (B...
John Sartori, Rakesh Kumar
FPL
2003
Springer
259views Hardware» more  FPL 2003»
13 years 9 months ago
Branch Optimisation Techniques for Hardware Compilation
Abstract. This paper explores using information about program branch probabilities to optimise reconfigurable designs. The basic premise is to promote utilization by dedicating mo...
Henry Styles, Wayne Luk
EMSOFT
2003
Springer
13 years 9 months ago
Heterogeneous Reactive Systems Modeling and Correct-by-Construction Deployment
Abstract. We propose a mathematical framework to deal with the composition of heterogeneous reactive systems. Our theory allows to establish theorems, from which design techniques ...
Albert Benveniste, Luca P. Carloni, Paul Caspi, Al...
ICRA
2003
IEEE
130views Robotics» more  ICRA 2003»
13 years 9 months ago
Design and modeling of classes of spatial reactionless manipulators
Abstract – For conventional designs of robots, manipulator motions result in forces and moments on the base. These forces and moments may cause undesirable translation and rotati...
Abbas Fattah, Sunil Kumar Agrawal
GECCO
2005
Springer
119views Optimization» more  GECCO 2005»
13 years 10 months ago
Automated re-invention of six patented optical lens systems using genetic programming
This paper describes how genetic programming was used as an invention machine to automatically synthesize complete designs for six optical lens systems that duplicated the functio...
John R. Koza, Sameer H. Al-Sakran, Lee W. Jones
ISCAS
2005
IEEE
191views Hardware» more  ISCAS 2005»
13 years 10 months ago
Behavioural modeling and simulation of a switched-current phase locked loop
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
Peter R. Wilson, Reuben Wilcock
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
13 years 10 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...
MTV
2007
IEEE
121views Hardware» more  MTV 2007»
13 years 10 months ago
Chico: An On-chip Hardware Checker for Pipeline Control Logic
The widening gap between CPU complexity and verification capability is becoming increasingly more salient. It is impossible to completely verify the functionality of a modern mic...
Andrew DeOrio, Adam Bauserman, Valeria Bertacco