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DFT
2004
IEEE
101views VLSI» more  DFT 2004»
11 years 10 months ago
Designs for Reducing Test Time of Distributed Small Embedded SRAMs
This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (eSRAMs). This architecture improves the one proposed in [4, 5]. The improv...
Baosheng Wang, Yuejian Wu, André Ivanov
DFT
2004
IEEE
134views VLSI» more  DFT 2004»
11 years 10 months ago
On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars
Defect tolerance is an extremely important aspect in nano-scale electronics as the bottom-up selfassembly fabrication process results in a significantly higher defect density comp...
Jing Huang, Mehdi Baradaran Tahoori, Fabrizio Lomb...
DFT
2004
IEEE
118views VLSI» more  DFT 2004»
11 years 10 months ago
Defect Characterization for Scaling of QCA Devices
Quantum dot Cellular Automata (QCA) is amongst promising new computing scheme in the nano-scale regimes. As an emerging technology, QCA relies on radically different operations in...
Jing Huang, Mariam Momenzadeh, Mehdi Baradaran Tah...
DFT
2004
IEEE
90views VLSI» more  DFT 2004»
11 years 10 months ago
An XOR Based Reed-Solomon Algorithm for Advanced RAID Systems
In this paper, a simple codec algorithm based on Reed-Solomon (RS) codes is proposed for erasure correcting in RAID (Redundant Array of Independent Disks) level 6 systems. Unlike ...
Ping-Hsun Hsieh, Ing-Yi Chen, Yu-Ting Lin, Sy-Yen ...
DFT
2004
IEEE
114views VLSI» more  DFT 2004»
11 years 10 months ago
Characteristics of Fault-Tolerant Photodiode and Photogate Active Pixel Sensor (APS)
Reliability and manufacturing costs due to defects is a significant problem with image sensors and the ability to recover from a fault would alleviate some of these costs. A fault...
Michelle L. La Haye, Glenn H. Chapman, Cory Jung, ...
DFT
2004
IEEE
94views VLSI» more  DFT 2004»
11 years 10 months ago
Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes
This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output encoder based on check matrix of a (n, n1, m, 3) convolutional...
Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman ...
DFT
2004
IEEE
78views VLSI» more  DFT 2004»
11 years 10 months ago
Reliability Modeling and Assurance of Clockless Wave Pipeline
This paper presents theoretical yet practical methodologies to model, assure and optimize the Reliability of Clockless Wave Pipeline. Clockless wave pipeline is a cutting-edge and...
T. Feng, Nohpill Park, Yong-Bin Kim, Fabrizio Lomb...
DFT
2004
IEEE
95views VLSI» more  DFT 2004»
11 years 10 months ago
Mixed Loopback BiST for RF Digital Transceivers
In this paper we analyze the performance of a mixed built-in-self-test (BiST) for RF IC digital transceivers, where a baseband processor can be used both as a test pattern generat...
Jerzy Dabrowski, Javier Gonzalez Bayon
DFT
2004
IEEE
93views VLSI» more  DFT 2004»
11 years 10 months ago
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Rayc...
DFT
2004
IEEE
102views VLSI» more  DFT 2004»
11 years 10 months ago
Exploiting an I-IP for In-Field SOC Test
Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza ...
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