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DFT
2006
IEEE
148views VLSI» more  DFT 2006»
9 years 4 months ago
Bilateral Testing of Nano-scale Fault-tolerant Circuits
As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. ...
Lei Fang, Michael S. Hsiao
DFT
2006
IEEE
85views VLSI» more  DFT 2006»
9 years 6 months ago
Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects
With the recent development of nanoscale materials and assembly techniques, it is envisioned to build high-density reconfigurable systems which have never been achieved by the pho...
Yadunandana Yellambalase, Minsu Choi, Yong-Bin Kim
DFT
2006
IEEE
122views VLSI» more  DFT 2006»
9 years 6 months ago
Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design
The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synch...
Minsu Choi, Myungsu Choi, Zachary D. Patitz, Nohpi...
DFT
2006
IEEE
143views VLSI» more  DFT 2006»
9 years 8 months ago
Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...
Vijay K. Jain, Glenn H. Chapman
DFT
2006
IEEE
92views VLSI» more  DFT 2006»
9 years 8 months ago
Low-Cost Hardening of Image Processing Applications Against Soft Errors
Image processing systems are increasingly used in safetycritical applications, and their hardening against soft errors becomes an issue. We propose a methodology to identify soft ...
Ilia Polian, Bernd Becker, Masato Nakasato, Satosh...
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
9 years 8 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
DFT
2006
IEEE
99views VLSI» more  DFT 2006»
9 years 8 months ago
Error Tolerance of DNA Self-Assembly by Monomer Concentration Control
Abstract— This paper proposes the control of monomer concentration as a novel improvement of the kinetic Tile Assembly Model (kTAM) to reduce the error rate in DNA selfassembly. ...
Byunghyun Jang, Yong-Bin Kim, Fabrizio Lombardi
DFT
2006
IEEE
130views VLSI» more  DFT 2006»
9 years 8 months ago
Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream
Control flow checking (CFC) is a well known concurrent checking technique for ensuring that a program’s instruction execution sequence follows permissible paths. Almost all CFC...
Federico Rota, Shantanu Dutt, Sahithi Krishna
DFT
2006
IEEE
77views VLSI» more  DFT 2006»
9 years 8 months ago
Fault Tolerant Active Pixel Sensors in 0.18 and 0.35 Micron Technologies
A Fault Tolerant Active Pixel Sensor (FTAPS) has been designed and fabricated to correct for point defects that occur in CMOS image sensors both at manufacturing and over the life...
Michelle L. La Haye, Cory Jung, David Chen, Glenn ...
DFT
2006
IEEE
82views VLSI» more  DFT 2006»
9 years 8 months ago
VLSI Implementation of a Fault-Tolerant Distributed Clock Generation
In this paper we will introduce a novel approach for the on-chip generation of a faulttolerant clock. We will motivate why it becomes more and more desirable to provide VLSI circu...
Markus Ferringer, Gottfried Fuchs, Andreas Steinin...
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