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DFT
2008
IEEE
149views VLSI» more  DFT 2008»
10 years 4 months ago
Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?
Side-channel attacks are nowadays a serious concern when implementing cryptographic algorithms. Powerful ways for gaining information about the secret key as well as various count...
Francesco Regazzoni, Thomas Eisenbarth, Luca Breve...
DFT
2008
IEEE
151views VLSI» more  DFT 2008»
10 years 4 months ago
Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller
This paper presents a concurrent error detection technique for the control logic of a modern microprocessor. Our method is based on execution time prediction for each instruction ...
Michail Maniatakos, Naghmeh Karimi, Yiorgos Makris...
DFT
2008
IEEE
182views VLSI» more  DFT 2008»
10 years 4 months ago
Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis
This paper addresses a new threat to the security of integrated circuits (ICs). The migration of IC fabrication to untrusted foundries has made ICs vulnerable to malicious alterat...
Xiaoxiao Wang, Hassan Salmani, Mohammad Tehranipoo...
DFT
2008
IEEE
89views VLSI» more  DFT 2008»
10 years 9 months ago
Fabrication Variations and Defect Tolerance for Nanomagnet-Based QCA
Tolerating defects and fabrication variations will be critical in any system made with devices that have nanometer feature sizes. This paper considers how fabrication variations a...
Michael T. Niemier, Michael Crocker, Xiaobo Sharon...
DFT
2008
IEEE
117views VLSI» more  DFT 2008»
10 years 9 months ago
Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS
With each technology node shrink, a silicon chip becomes more susceptible to soft errors. The susceptibility further increases as the voltage is scaled down to save energy. Based ...
Vikas Chandra, Robert C. Aitken
DFT
2008
IEEE
86views VLSI» more  DFT 2008»
10 years 9 months ago
On Reducing Circuit Malfunctions Caused by Soft Errors
Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, Xu...
DFT
2008
IEEE
107views VLSI» more  DFT 2008»
10 years 9 months ago
Checkpointing of Rectilinear Growth in DNA Self-Assembly
Error detection/correction techniques have been advocated for algorithmic self-assembly. Under rectilinear growth, it requires only two additional tiles, generally referred to as ...
Stephen Frechette, Yong-Bin Kim, Fabrizio Lombardi
DFT
2008
IEEE
103views VLSI» more  DFT 2008»
10 years 9 months ago
Arbitrary Error Detection in Combinational Circuits by Using Partitioning
The paper presents a new technique for designing a concurrently checking combinational circuit. The technique is based on partitioning the circuit into two independent sub-circuit...
Osnat Keren, Ilya Levin, Vladimir Ostrovsky, Beni ...
DFT
2008
IEEE
82views VLSI» more  DFT 2008»
10 years 9 months ago
Selective Hardening of NanoPLA Circuits
Nanoelectronic components are expected to suffer from very high error rates, implying the need for hardening techniques. We propose a fine-grained approach to harden a promising...
Ilia Polian, Wenjing Rao
DFT
2008
IEEE
86views VLSI» more  DFT 2008»
10 years 9 months ago
Enhancing Silicon Debug via Periodic Monitoring
Scan-based debug methods give high observability of internal signals, however, they require halting the system to scan out responses from the circuit-under-debug (CUD). This is ti...
Joon-Sung Yang, Nur A. Touba
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