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DFT
2009
IEEE
210views VLSI» more  DFT 2009»
8 years 7 months ago
Optimizing Parametric BIST Using Bio-inspired Computing Algorithms
Optimizing the BIST configuration based on the characteristics of the design under test is a complicated and challenging work for test engineers. Since this problem has multiple o...
Nastaran Nemati, Amirhossein Simjour, Amirali Ghof...
DFT
2009
IEEE
139views VLSI» more  DFT 2009»
8 years 7 months ago
Reduced Precision Checking for a Floating Point Adder
We present an error detection technique for a floating point adder which uses a checker adder of reduced precision to determine if the result is correct within some error bound. O...
Patrick J. Eibl, Andrew D. Cook, Daniel J. Sorin
DFT
2009
IEEE
106views VLSI» more  DFT 2009»
8 years 11 months ago
Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points
Recently, a new test point insertion method for pseudo-random built-in self-test (BIST) was proposed in [Yang 09] which tries to use functional flip-flops to drive control test po...
Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba
DFT
2009
IEEE
178views VLSI» more  DFT 2009»
8 years 11 months ago
Soft Core Embedded Processor Based Built-In Self-Test of FPGAs
This paper presents the first implementation of Built-In Self-Test (BIST) of Field Programmable Gate Arrays (FPGAs) using a soft core embedded processor for reconfiguration of the...
Bradley F. Dutton, Charles E. Stroud
DFT
2009
IEEE
175views VLSI» more  DFT 2009»
8 years 11 months ago
Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories
Hybrid CMOS/non-CMOS memories, in short hybrid memories, have been lauded as future ultra-capacity data memories. Nonetheless, such memories are going to suffer from high degree o...
Nor Zaidi Haron, Said Hamdioui
DFT
2009
IEEE
154views VLSI» more  DFT 2009»
8 years 11 months ago
Dual-Layer Cooperative Error Control for Reliable Nanoscale Networks-on-Chip
We propose a framework that allows dual-layer cooperative error control in a nanoscale network-on-chip (NoC), to simultaneously improve reliability, performance and energy efficie...
Qiaoyan Yu, Paul Ampadu
DFT
2009
IEEE
127views VLSI» more  DFT 2009»
8 years 11 months ago
A Sensor to Detect Normal or Reverse Temperature Dependence in Nanoscale CMOS Circuits
The temperature dependence of MOSFET drain current varies with supply voltage. Two distinct voltage regions exist—a normal dependence (ND) region where an increase in temperatur...
David Wolpert, Paul Ampadu
DFT
2009
IEEE
155views VLSI» more  DFT 2009»
8 years 11 months ago
Errors in DNA Self-Assembly by Synthesized Tile Sets
This paper presents a study of errors that occur in DNA self-assembly using synthesized tile sets for template manufacturing. It is shown that due to the reduced size, aggregates ...
Xiaojun Ma, Masoud Hashempour, Yong-Bin Kim, Fabri...
DFT
2009
IEEE
189views VLSI» more  DFT 2009»
8 years 11 months ago
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms
Pre-fabrication design verification and post-fabrication chip testing are two important stages in the product realization process. These two stages consume a large part of resourc...
Meng Zhang, Anita Lungu, Daniel J. Sorin
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