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    HPCA
    2001
    IEEE
    99views Distributed And Parallel Com...» more  HPCA 2001»
    Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
    14 years 5 months ago
    Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
    Download  impact.asu.edu
    In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
    Wei-Fen Lin, Steven K. Reinhardt, Doug Burger
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