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RTAS
2010
IEEE
10 years 11 months ago
Using PCM in Next-generation Embedded Space Applications
Abstract--Dynamic RAM (DRAM) has been the best technology for main memory for over thirty years. In embedded space applications, radiation hardened DRAM is needed because gamma ray...
Alexandre Peixoto Ferreira, Bruce R. Childers, Ram...
MICRO
2010
IEEE
154views Hardware» more  MICRO 2010»
10 years 11 months ago
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory
High density memory is becoming more important as many execution streams are consolidated onto single chip many-core processors. DRAM is ubiquitous as a main memory technology, but...
Jeffrey Stuecheli, Dimitris Kaseridis, Hillery C. ...
ISLPED
2010
ACM
128views Hardware» more  ISLPED 2010»
10 years 11 months ago
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
DRAM power and energy efficiency considerations are becoming increasingly important for low-power and mobile systems. Using lower power modes provided by commodity DRAM chips redu...
Ahmed M. Amin, Zeshan Chishti
MICRO
2010
IEEE
186views Hardware» more  MICRO 2010»
10 years 11 months ago
Phase-Change Technology and the Future of Main Memory
As DRAM and other charge memories reach scaling limits, resistive memories, such as phase change memory (PCM), may permit continued scaling of main memories. However, while PCM ma...
Benjamin C. Lee, Ping Zhou, Jun Yang 0002, Youtao ...
TVLSI
2002
102views more  TVLSI 2002»
11 years 27 days ago
Power-optimal encoding for a DRAM address bus
This paper presents an irredundant encoding technique to minimize the switching activity on a multiplexed Dynamic RAM (DRAM) address bus. The DRAM switching activity can be classif...
Wei-Chung Cheng, Massoud Pedram
SIGMETRICS
2008
ACM
11 years 1 months ago
DRAM is plenty fast for wirespeed statistics counting
Per-flow network measurement at Internet backbone links requires the efficient maintanence of large arrays of statistics counters at very high speeds (e.g. 40 Gb/s). The prevailin...
Bill Lin, Jun (Jim) Xu
JEC
2006
71views more  JEC 2006»
11 years 1 months ago
Destructive-read in embedded DRAM, impact on power consumption
This paper explores power consumption for destructive-read embedded DRAM. Destructive-read DRAM is based on conventional DRAM design, but with sense amplifiers optimized for lower ...
Haakon Dybdahl, Per Gunnar Kjeldsberg, Marius Gran...
CACM
2010
145views more  CACM 2010»
11 years 1 months ago
Phase change memory architecture and the quest for scalability
Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as dynamic random access memory (DRAM). In cont...
Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burg...
ECRTS
2010
IEEE
11 years 2 months ago
Making DRAM Refresh Predictable
Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Sched...
Balasubramanya Bhat, Frank Mueller
ASPLOS
2010
ACM
11 years 4 months ago
Micro-pages: increasing DRAM efficiency with locality-aware data placement
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
Kshitij Sudan, Niladrish Chatterjee, David Nellans...
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