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DSD
2003
IEEE
107views Hardware» more  DSD 2003»
11 years 7 months ago
DYNORA: A New Caching Technique
Cache design for high performance computing requires the realization of two seemingly disjoint goals of higher hit ratios at reduced access times. Recent research advocates the us...
P. Srivatsan, P. B. Sudarshan, P. P. Bhaskaran
DSD
2003
IEEE
123views Hardware» more  DSD 2003»
11 years 7 months ago
Design Tools and Reusable Libraries for FPGA-Based Digital Circuits
This paper suggests tools that provide significant improvements in the design and verification of FPGAbased digital circuits. These tools include reusable specifications of hardwa...
Valery Sklyarov, Iouliia Skliarova, Pedro Almeida,...
DSD
2003
IEEE
84views Hardware» more  DSD 2003»
11 years 7 months ago
A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits
Masanori Muroyama, Akihiko Hyodo, Takanori Okuma, ...
DSD
2003
IEEE
106views Hardware» more  DSD 2003»
11 years 7 months ago
Analytical Bounds on the Threads in IXP1200 Network Processor
Increasing link speeds have placed enormous burden on the processing requirements and the processors are expected to carry out a variety of tasks. Network Processors (NP) [1] [2] ...
S. T. G. S. Ramakrishna, H. S. Jamadagni
DSD
2003
IEEE
121views Hardware» more  DSD 2003»
11 years 7 months ago
CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors
With shrinking feature size of silicon fabrication technology, architects are putting more and more logic into a single die. While one might opt to use these transistors for build...
Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemi...
DSD
2003
IEEE
138views Hardware» more  DSD 2003»
11 years 7 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
DSD
2003
IEEE
108views Hardware» more  DSD 2003»
11 years 7 months ago
Concurrent Operation Scheduling and Unit Allocation with an Evolutionary Technique
This paper presents a method with an evolutionary approach to some of the tasks of integrated-circuit (IC) design. The work is focused on application-specific integrated circuits ...
Gregor Papa, Jurij Silc
DSD
2003
IEEE
100views Hardware» more  DSD 2003»
11 years 7 months ago
Fast Heuristics for the Edge Coloring of Large Graphs
Heuristic algorithms for coloring the edges of large undirected single-edge graphs with (or very close to) the minimal number of colors are presented. Compared to simulated anneal...
Mario Hilgemeier, Nicole Drechsler, Rolf Drechsler
DSD
2003
IEEE
109views Hardware» more  DSD 2003»
11 years 7 months ago
A methodology for the design of AHB bus master wrappers
This paper proposes a methodology and a basic structure for the design of wrappers used to adapt cores for use as bus masters. The AMBA AHB protocol is used as a case study in thi...
Marc Bertola, Guy Bois
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