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DSD
2006
IEEE
113views Hardware» more  DSD 2006»
13 years 6 months ago
Cascade Scheme for Concurrent Errors Detection
The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades f...
Ilya Levin, Vladimir Ostrovsky, Osnat Keren, Vladi...
DSD
2006
IEEE
135views Hardware» more  DSD 2006»
13 years 8 months ago
Hardware-Software Codesign of a Vector Co-processor for Public Key Cryptography
Until now, most cryptography implementations on parallel architectures have focused on adapting the software to SIMD architectures initially meant for media applications. In this ...
Jacques J. A. Fournier, Simon W. Moore
DSD
2006
IEEE
131views Hardware» more  DSD 2006»
13 years 8 months ago
Designing Efficient Irregular Networks for Heterogeneous Systems-on-Chip
Abstract-- Networks-on-Chip will serve as the central integration platform in future complex SoC designs, composed of a large number of heterogeneous processing resources. Most res...
Christian Neeb, Norbert Wehn
DSD
2006
IEEE
174views Hardware» more  DSD 2006»
13 years 8 months ago
Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering
Title of thesis: Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering Alokika Dash, Master of Science, 2006 Thesis dire...
Alokika Dash, Peter Petrov
DSD
2006
IEEE
83views Hardware» more  DSD 2006»
13 years 8 months ago
Resource-Efficient Routing and Scheduling of Time-Constrained Network-on-Chip Communication
Abstract. Network-on-chip-based multiprocessor systems-onchip are considered as future embedded systems platforms. One of the steps in mapping an application onto such a parallel p...
Sander Stuijk, Twan Basten, Marc Geilen, Amir Hoss...
DSD
2006
IEEE
99views Hardware» more  DSD 2006»
13 years 8 months ago
Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads
We present a flexible method for bus and network on chip performance analysis, which is based on the adaptation of workload models to resemble various applications. Our analysis m...
Rikard Thid, Ingo Sander, Axel Jantsch
DSD
2006
IEEE
98views Hardware» more  DSD 2006»
13 years 8 months ago
Profiling Bluetooth and Linux on the Xilinx Virtex II Pro
In this paper, we present profiling results of the Bluetooth standard implemented on the Xilinx Virtex II Pro device. The investigation is performed in two stages. First, we solel...
Filipa Duarte, Stephan Wong
DSD
2006
IEEE
95views Hardware» more  DSD 2006»
13 years 8 months ago
Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication
We present a performance-oriented refinement approach that refines a perfectly synchronous communication model onto Network-on-Chip (NoC) communication. We first identify four bas...
Zhonghai Lu, Ingo Sander, Axel Jantsch
DSD
2006
IEEE
126views Hardware» more  DSD 2006»
13 years 10 months ago
Off-Line Testing of Delay Faults in NoC Interconnects
Testing of high density SoCs operating at high clock speeds is an important but difficult problem. Many faults, like delay faults, in such sub-micron chips may only appear when th...
Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimu...
DSD
2006
IEEE
116views Hardware» more  DSD 2006»
13 years 10 months ago
Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems*
In this paper we present an approach for the mapping optimization of fault-tolerant embedded systems for safetycritical applications. Processes and messages are statically schedul...
Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Pe...