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DSD
2009
IEEE
141views Hardware» more  DSD 2009»
9 years 5 days ago
A Reconfigurable Frame Interpolation Hardware Architecture for High Definition Video
-- Since Frame Rate Up-Conversion (FRC) is started to be used in recent consumer electronics products like High Definition TV, real-time and low cost implementation of FRC algorith...
Ozgur Tasdizen, Ilker Hamzaoglu
DSD
2009
IEEE
93views Hardware» more  DSD 2009»
9 years 5 days ago
Transactions Sequence Tracking by means of Dynamic Binary Instrumentation of TLM Models
Several traditional VHDL fault injection mechanisms like mutants or saboteurs have been adapted to SystemC model descriptions. The main drawback of these approaches is the necessi...
Antonio da Silva, Sebastian Sanchez
DSD
2009
IEEE
88views Hardware» more  DSD 2009»
9 years 5 days ago
A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor
Abstract--The implementation of an efficient result forwarding unit for asynchronous processors faces the problem of the inherent lack of synchronisation between result producer an...
Luis A. Tarazona, Doug A. Edwards, Luis A. Plana
DSD
2009
IEEE
118views Hardware» more  DSD 2009»
9 years 5 months ago
On the Risk of Fault Coupling over the Chip Substrate
—Duplication and comparison has proven to be an efficient method for error detection. Based on this generic principle dual core processor architectures with output comparison ar...
Peter Tummeltshammer, Andreas Steininger
DSD
2009
IEEE
83views Hardware» more  DSD 2009»
9 years 5 months ago
Streaming Reduction Circuit
—Reduction circuits are used to reduce rows of floating point values to single values. Binary floating point operators often have deep pipelines, which may cause hazards when m...
Marco Gerards, Jan Kuper, André B. J. Kokke...
DSD
2009
IEEE
106views Hardware» more  DSD 2009»
9 years 6 months ago
Model-Driven Design of Embedded Multimedia Applications on SoCs
This paper addresses the design issue of System-onelevating the design abstraction levels, through a model-driven approach. It considers the standard Marte profile, which is dedic...
Adolf Abdallah, Abdoulaye Gamatié, Jean-Luc...
DSD
2009
IEEE
126views Hardware» more  DSD 2009»
9 years 6 months ago
Architecture-Driven Synthesis of Reconfigurable Cells
In this paper, we present a novel method for merging sets of computational patterns into a reconfigurable cell respecting design constraints and optimizing specific design aspects...
Christophe Wolinski, Krzysztof Kuchcinski, Erwan R...
DSD
2009
IEEE
147views Hardware» more  DSD 2009»
9 years 6 months ago
A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computat...
Abdulkadir Akin, Yigit Dogan, Ilker Hamzaoglu
DSD
2009
IEEE
152views Hardware» more  DSD 2009»
9 years 6 months ago
ARROW - A Generic Hardware Fault Injection Tool for NoCs
Todays NoCs are reaching a level where it is getting very hard to ensure 100% of functionality. Consequently, fault tolerance has become an important aspect in todays design techn...
Michael Birner, Thomas Handl
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