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DSD
2010
IEEE
162views Hardware» more  DSD 2010»
13 years 2 months ago
A Parallel for Loop Memory Template for a High Level Synthesis Compiler
—We propose a parametrized memory template for applications with parallel for loops. The template’s parameters reflect important trade-offs made during system design. The temp...
Craig Moore, Wim Meeus, Harald Devos, Dirk Strooba...
DSD
2010
IEEE
144views Hardware» more  DSD 2010»
13 years 3 months ago
On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism
—Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated i...
Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen
DSD
2010
IEEE
135views Hardware» more  DSD 2010»
13 years 3 months ago
An Approximate Maximum Common Subgraph Algorithm for Large Digital Circuits
—This paper presents an approximate Maximum Common Subgraph (MCS) algorithm, specifically for directed, cyclic graphs representing digital circuits. Because of the application d...
Jochem H. Rutgers, Pascal T. Wolkotte, Philip K. F...
DSD
2010
IEEE
123views Hardware» more  DSD 2010»
13 years 3 months ago
A Packet Classifier Using a Parallel Branching Program Machine
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
DSD
2010
IEEE
161views Hardware» more  DSD 2010»
13 years 3 months ago
Design of Trace-Based Split Array Caches for Embedded Applications
—Since many embedded systems execute a predefined set of programs, tuning system components to application programs and data is the approach chosen by many design techniques to o...
Alice M. Tokarnia, Marina Tachibana
DSD
2010
IEEE
110views Hardware» more  DSD 2010»
13 years 3 months ago
A Predictable Multiprocessor Design Flow for Streaming Applications with Dynamic Behaviour
—The design of new embedded systems is getting more and more complex as more functionality is integrated into these systems. To deal with the design complexity, a predictable des...
Sander Stuijk, Marc Geilen, Twan Basten
DSD
2010
IEEE
134views Hardware» more  DSD 2010»
13 years 3 months ago
A New High-Level Methodology for Programming FPGA-Based Smart Camera
Due to the various devices composing a smart camera system, various languages have to be known by the designer (like HDL and C/C++). Most of vision applications designers are soft...
Nicolas Roudel, François Berry, Jocelyn S&e...
DSD
2010
IEEE
140views Hardware» more  DSD 2010»
13 years 3 months ago
Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications
—Although many efficient high-level algorithms have been proposed for the realization of Multiple Constant Multiplications (MCM) using the fewest number of addition and subtract...
Levent Aksoy, Eduardo Costa, Paulo F. Flores, Jos&...
DSD
2010
IEEE
153views Hardware» more  DSD 2010»
13 years 3 months ago
Simulation of High-Performance Memory Allocators
—Current general-purpose memory allocators do not provide sufficient speed or flexibility for modern highperformance applications. To optimize metrics like performance, memory us...
José Luis Risco-Martín, José ...
DSD
2010
IEEE
126views Hardware» more  DSD 2010»
13 years 3 months ago
Low Power FPGA Implementations of 256-bit Luffa Hash Function
Low power techniques in a FPGA implementation of the hash function called Luffa are presented in this paper. This hash function is under consideration for adoption as standard. Tw...
Paris Kitsos, Nicolas Sklavos, Athanassios N. Skod...