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TVLSI
2002
94views more  TVLSI 2002»
13 years 4 months ago
A network flow approach to memory bandwidth utilization in embedded DSP core processors
This paper presents a network flow approach to solving the register binding and allocation problem for multiword memory access DSP processors. In recently announced DSP processors,...
Catherine H. Gebotys
CDES
2006
118views Hardware» more  CDES 2006»
13 years 6 months ago
New DSP Benchmark based on Selectable Mode Vocoder (SMV)
Digital signal processing (DSP) industry has been growing rapidly over the past few years; it remains the technology driver for the recovering semiconductor industry. Performance ...
Erh-Wen Hu, Cyril Ku, Andrew Russo, Bogong Su, Jia...
FPL
1995
Springer
129views Hardware» more  FPL 1995»
13 years 8 months ago
An Assessment of the Suitability of FPGA-Based Systems for Use in Digital Signal Processing
Abstract. FPGAs have been proposed as high-performance alternatives to DSP processors. This paper quantitatively compares FPGA performance against DSP processors and ASICs using ac...
Russell J. Petersen, Brad L. Hutchings
ISSS
1996
IEEE
103views Hardware» more  ISSS 1996»
13 years 8 months ago
Instruction Set Design and Optimizations for Address Computation in DSP Architectures
In this paper we investigate the problem of code generation for address computation for DSP processors. This work is divided into four parts. First, we propose a branch instructio...
Guido Araujo, Ashok Sudarsanam, Sharad Malik
CC
2003
Springer
192views System Software» more  CC 2003»
13 years 9 months ago
Address Register Assignment for Reducing Code Size
Abstract. In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance since studies of programs have shown that in...
Mahmut T. Kandemir, Mary Jane Irwin, Guilin Chen, ...
LCPC
2005
Springer
13 years 10 months ago
Compiler Supports and Optimizations for PAC VLIW DSP Processors
Abstract. Compiler is substantially regarded as the most essential component in the software toolchain to promote a successful processor design. This paper describes our preliminar...
Yung-Chia Lin, Chung-Lin Tang, Chung-Ju Wu, Ming-Y...